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| structure silicon gate cmos ic absolute maximum ratings supply voltage v dd ?.3 to +7.0 v input voltage v i ?.3 to +7.0 v (v ss ?0.3v to v dd +0.3v) output voltage v o ?.3 to +7.0 v storage temperature tstg ?0 to +125 ? supply voltage difference v ss ?av ss ?.3 to +0.3 v v dd ?av dd ?.3 to +0.3 v recommended operating conditions supply voltage operating temperature * the v dd (min.) for the CXD2586R/-1 varies according to the playback speed and built-in vco selection. the v dd (min.) is 4.5v when high-speed vco and quadruple-speed playback are selected (variable pitch off). the v dd (min.) for the CXD2586R/-1 under various conditions are as shown in the following table. ?1 CXD2586R/-1 144 pin lqfp (plastic) e95y01a65-st cd digital signal processor with built-in digital servo and dac description the CXD2586R/-1 is a digital signal processor lsi for cd players. this lsi incorporates the digital servo, digital filter and 1-bit dac. features all digital signal processing during playback is performed with a single chip highly integrated mounting possible due to a built- in ram digital signal processor block playback mode which supports cav (constant angular velocity) frame jitter free half-speed to octuple-speed continuous playback possible with a low external clock (only CXD2586R-1 supports up to octuple speed) allows relative rotational velocity readout wide capture range playback mode spindle rotational velocity following method supports normal-speed, double-speed, quadruple- speed, sextuple-speed and octuple-speed playback (only CXD2586R-1) wide frame jitter margin ( 28 frames) due to a built-in 32k ram the bit clock, which strobes the efm signal, is generated by the digital pll efm data demodulation enhanced efm frame sync signal protection refined super strategy-based powerful error correction c1: double correction, c2: quadruple correction octuple-speed (only CXD2586R-1), sextuple-speed, quadruple-speed and double-speed playback (digital signal processor and digital servo blocks) noise reduction during track jumps auto zero-cross mute subcode demodulation and sub q data error detection digital spindle servo (with oversampling filter) 16-bit traverse counter asymmetry compensation circuit cpu interface on serial bus error correction monitor signal, etc. output from a new cpu interface servo auto sequencer fine search performs track jumps with high accuracy digital audio interface outputs digital level meter, peak meter bilingual compatible digital servo block microcomputer software-based flexible servo control servo error signal, offset cancel function servo loop, auto gain control function e:f balance, focus bias adjustment function digital filters (dac and lpf blocks) low-pass filter for dac digital de-emphasis digital attenuation 4fs oversampling filter adopts secondary ? noise shaper lpf for dac analog output playback speed 8 (only CXD2586R-1) 6 4 2 * 1 2 1 * 2 1 4.75 4.50 4.50 4.00 3.40 3.40 3.40 4.00 3.40 3.40 4.50 vco1 high speed vco1 normal speed dac block v dd (min.) [v] ? dashes indicate that there is no assurance of the processor operating. all values are for variable pitch off. * 1 when the internal operation of the lsi is set to normal- speed playback and the operating clock of the signal processor is doubled, double-speed playback results. * 2 when the internal operation of the lsi is set to double- speed mode and the crystal oscillating frequency is halved in low power consumption mode, normal-speed playback results. sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits.
?2 CXD2586R/-1 block diagram error corrector noise shaper peak detector opamp anasw a/d converter 32k ram serial/parallel processor digital pll vari-pitch double speed mux * clv processor 18-times oversampling filter mirr servo interface pwm generator focus pwm generator tracking pwm generator sled pwm generator clock generator subcode p to w processor timing generator1 subcode q processor servo auto sequencer cpu interface 4fs digital filter + 1 bit dac efm demodulator sync protector priority encoder d/a data processor digital out register address generator timing generator2 servo dsp focus servo tracking servo sled servo mcko mclk vcki fsto c4m c16m pdo vcoi vcoo pco fili filo cltv rfac asyi asyo asye wfck scor mon fsw mdp mds exck sbso sqck sqso ain1 lout1 aout2 ain2 sfdr, sfon srdr, sron tfdr, tfon trdr, tron ffdr, ffon frdr, fron sens pssl da01 to da16 mute cout mirr dfct fok data clok xlat dout md2 rfdc te se fe test tes2 tes3 dv dd 0 dv dd 2 av dd 1 av dd 2 av dd 3 av dd 4 av dd 5 dv ss 1 dv ss 2 av ss 1 av ss 2 av ss 31 av ss 32 av ss 41 xrst rfc adio xtlo xtli vpco1 dts4 dts5 dts6 pcmdi bcki lrcki 8 dfct fok 2 2 2 2 2 2 vc ce osc pwmi v16m vctl dts1 dts2 dts3 dts7 aout1 lout2 lpf lpf vpco2 acdt xtsl dac block signal processor block servo block 2 3 4 5 6 7 8 9 10 12 14 15 19 20 23 25 27 47 48 49 52 53 56 57 58 68 67 63 64 65 66 62 72 73 74 82 83 84 76 77 78 88 87 86 85 79 80 89 99 98 97 96 91 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 11 0 111 127 12 8 12 9 131 132 13 4 13 5 13 6 14 0 141 14 2 14 3 14 4 16 18 43 45 46 50 51 54 55 59 60 81 10 1 12 6 13 0 137 13 9 11 dv dd 3 dv ss 3 av ss 42 av ss 5 124, 123 122, 125 120, 119 118, 121 116, 115 114, 117 42 to 31, 29, 28, 26, 24 vpco1, 2 4, 5 ?3 CXD2586R/-1 pin configuration 36 35 34 31 32 33 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 40 39 38 37 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 97 96 95 94 91 92 93 10 0 99 98 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 73 74 81 82 83 84 75 76 77 78 88 87 86 85 79 80 89 90 111 10 9 11 0 112 113 114 115 116 117 11 8 119 12 0 121 12 2 12 3 124 12 5 12 6 127 12 8 12 9 13 0 131 132 13 3 13 4 13 5 13 6 137 13 8 13 9 14 0 141 14 2 14 3 14 4 av ss 31 av ss 5 xtli xtlo av dd 5 av ss 42 lout2 ain2 av dd 4 av ss 41 nc. dv ss 1 da01 da02 da03 da04 da05 da06 se fe vc filo fili pco cltv av ss 1 rfac bias asyi asyo av dd 1 nc. dv dd 1 asye pssl wdck lrck lrcki da16 pcmdi da15 bcki da14 da13 da12 da11 da10 da09 da08 da07 lock sstp sfdr sron srdr sfon tfdr tron trdr tfon ffdr fron frdr ffon dv dd 3 vcoo vcoi test dv ss 3 tes2 tes3 nc. pdo vcki v16m av dd 2 igen av ss 2 adio rfc rfdc ce te mds mon fsw testa fok dfct mirr nc. cout c4m clok xlat data atsk dfsw sclk dirc sens sqck sqso exck sbso scor wfck mute dout md2 c16m fsto fsti mclk dts6 dts5 dts4 dts3 dts2 dts1 nc. av ss 32 av dd 3 aout1 ain1 lout1 das1 das0 xwo dts7 xtsl aout2 pwmi dv dd 2 xrst nc. dv ss 2 mcko mdp nc. vpco2 vctl vpco1 nc. ?4 CXD2586R/-1 pin description pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 i i i o o i o i o i i i i o i i o o i o i o i o o o o o o o o 1, z, 0 1, z, 0 analog 1, z, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 sled error signal input. focus error signal input. center voltage input. wide-band efm pll vco2 charge pump output. wide-band efm pll vco2 charge pump output. wide-band efm pll vco2 control voltage input. master pll filter output (slave = digital pll). master pll filter input. master pll charge pump output. master vco control voltage input. analog gnd. efm signal input. asymmetry circuit constant current input. asymmetry comparator voltage input. efm full-swing output (low = v ss , high = v dd ). analog power supply. digital power supply. asymmetry circuit on/off (low = off, high = on). audio data output mode switching input (low = serial, high = parallel). d/a interface for 48-bit slot. word clock f = 2fs. d/a interface for 48-bit slot. lr clock f = fs. lr clock input to dac (48-bit slot). da16 (msb) output when pssl = 1, 48-bit slot serial data output (two's complement, msb first) when pssl = 0. audio data input to dac (48-bit slot). da15 output when pssl = 1, 48-bit slot bit clock output when pssl = 0. bit clock input to dac (48-bit slot). da14 output when pssl = 1, 64-bit slot serial data output (two's complement, lsb first) when pssl = 0. da13 output when pssl = 1, 64-bit slot bit clock output when pssl = 0. da12 output when pssl = 1, 64-bit slot lr clock output when pssl = 0. da11 output when pssl = 1, gtop output when pssl = 0. da10 output when pssl = 1, xugf output when pssl = 0. da09 output when pssl = 1, xplck output when pssl = 0. da08 output when pssl = 1, gfs output when pssl = 0. da07 output when pssl = 1, rfck output when pssl = 0. se fe vc vpco1 vpco2 vctl filo fili pco cltv av ss 1 rfac bias asyi asyo av dd 1 dv dd 1 asye pssl wdck lrck lrcki da16 pcmdi da15 bcki da14 da13 da12 da11 da10 da09 da08 da07 symbol i/o description ?5 CXD2586R/-1 pin no. 37 38 39 40 41 42 43 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 62 63 64 65 66 67 68 69 70 71 72 73 74 75 o o o o o o o i o o i o i o i i i i i i i o i i 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 analog analog 1, 0 analog analog 1, 0 da06 output when pssl = 1, c2po output when pssl = 0. da05 output when pssl = 1, xraof output when pssl = 0. da04 output when pssl = 1, mnt3 output when pssl = 0. da03 output when pssl = 1, mnt2 output when pssl = 0. da02 output when pssl = 1, mnt1 output when pssl = 0. da01 output when pssl = 1, mnt0 output when pssl = 0. digital gnd. analog gnd. analog power supply. channel 2 analog output. channel 2 analog input. channel 2 line output. analog gnd. master clock power supply. master clock 33.8688mhz crystal oscillation circuit output. master clock 33.8688mhz crystal oscillation circuit output. master clock gnd. analog gnd. channel 1 line output pin. channel 1 analog input pin. channel 1 analog output pin. analog power supply. analog gnd. dac test pin. normally fixed to high. dac test pin. normally fixed to high. dac test pin. leave this open. dac test pin. leave this open dac test pin. leave this open. dac test pin. leave this open. dac test pin. normally fixed to low. dac sync window open input. normally high, window open when low. dac test pin. normally fixed to low. dac test pin. normally fixed to low. crystal selection input. dsp clock output. dsp clock input. 2/3 frequency division input for mclk pin. da06 da05 da04 da03 da02 da01 dv ss 1 av ss 41 av dd 4 aout2 ain2 lout2 av ss 42 av dd 5 xtlo xtli av ss 5 av ss 31 lout1 ain1 aout1 av dd 3 av ss 32 dts1 dts2 dts3 dts4 dts5 dts6 dts7 xwo das0 das1 xtsl mcko mclk fsti symbol i/o description ?6 CXD2586R/-1 76 77 78 79 80 81 82 83 84 85 86 87 88 89 91 92 93 94 95 96 97 98 99 101 102 103 104 105 106 107 108 110 111 112 113 114 115 o o o i o i o o o i o i o i i i i i i i i o o o o i o o o o o i o o 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 z, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 2/3 frequency division output for mclk pin. does not change with variable pitch. 1/4 frequency division output for mclk pin. changes with variable pitch. 16.9344mhz output. changes simultaneously with variable pitch. digital out on/off control. (low: off, high: on) digital out output pin. digital gnd. mute (low: off, high: on) wfck (write flame clock) output. outputs a high signal when either subcode sync s0 or s1 is detected. sub p to w serial output. sbso readout clock input. sub q 80-bit and pcm peak and level data 16-bit output. sqso readout clock input. sens output to cpu. system reset. reset when low. used during 1-track jumps. sens serial data readout clock input. dfct switching pin. high: dfct countermeasure circuit off. anti-shock pin. serial data input from cpu. latch input from cpu. serial data is latched at the falling edge. serial data transfer clock input from cpu. track count signal output. digital power supply. mirror signal output. defect signal output. focus ok signal output. test pin. not connected. spindle motor external pin input. spindle motor output filter switching output. spindle motor on/off control output. spindle motor servo control output. spindle motor servo control output. gfs is sampled at 460hz; when gfs is high, this pin outputs a high signal. if gfs is low eight consecutive samples, this pin outputs low. disc innermost track detection signal input. sled drive output. sled drive output. fsto c4m c16m md2 dout dv ss 2 mute wfck scor sbso exck sqso sqck sens xrst dirc sclk dfsw atsk data xlat clok cout dv dd 2 mirr dfct fok testa pwmi fsw mon mdp mds lock sstp sfdr sron pin no. symbol i/o description ?7 CXD2586R/-1 * in the 144-pin lqfp, the following pins are nc: pins 17, 30, 44, 61, 90, 100, 109, and 133 notes) the 64-bit slot is an lsb first, two's complement output. the 48-bit slot is an msb first, two's complement output. gtop is used to monitor the frame sync protection status. (high: sync protection window released.) xugf is the negative pulse for the frame sync obtained from the efm signal. it is the signal before sync protection. xplck is the inverse of the efm pll clock. the pll is designed so that the falling edge and the efm signal transition point coincide. the gfs signal goes high when the frame sync and the insertion protection timing match. rfck is derived from the crystal accuracy, and has a cycle of 136 s. c2po represents the data error status. xraof is generated when the 32k ram exceeds the 28f jitter margin. 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 134 135 136 137 138 139 140 141 142 143 144 o o o o o o o o o o o i i i i o i o i o i i i i 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, z, 0 1, 0 sled drive output. sled drive output. tracking drive output. tracking drive output. tracking drive output. tracking drive output. focus drive output. focus drive output. focus drive output. focus drive output. digital power supply. analog efm pll oscillation circuit output. analog efm pll oscillation circuit input. flock = 8.6436mhz. test pin. normally fixed to low. digital gnd. test pin. normally fixed to low. test pin. normally fixed to low. analog efm pll charge pump output. variable pitch clock input from the external vco. fcenter = 16.9344mhz. wide-band efm pll vco2 oscillation output. analog power supply. operational amplifier current source reference resistance connection. analog gnd. operational amplifier output. rf signal lpf time constant capacitor connection. rf signal input. center servo analog input. tracking error signal input. srdr sfon tfdr tron trdr tfon ffdr fron frdr ffon dv dd 3 vcoo vcoi test dv ss 3 tes2 tes3 pdo vcki v16m av dd 2 igen av ss 2 adio rfc rfdc ce te pin no. symbol i/o description ?8 CXD2586R/-1 electrical characteristics 1. dc characteristics (v dd = av dd = 5.0v 10%, vss = avss = 0v, topr = ?0 to +75?) item input voltage (1) input voltage (2) input voltage (3) output voltage (1) output voltage (2) output voltage (1) output voltage (4) output voltage (5) input leak current (1) input leak current (2) input leak current (3) tri-state pin output leak current * 1 * 2 * 3 , 11 , 12 * 4 * 5 * 6 * 7 * 13 * 1 , 2 , 3 , 12 * 8 * 9 * 10 schmitt input analog input i oh = ?ma i ol = 4ma i oh = ?ma i ol = 4ma i ol = 4ma i oh = ?.28ma i ol = 0.36ma i oh = ?ma i ol = 8ma v i = 0 to 5.5v v i = 1.5 to 3.5v v i = 0 to 5.0v v o = 0 to 5.5v high level input voltage low level input voltage high level input voltage low level input voltage input voltage high level output voltage low level output voltage high level output voltage low level output voltage low level output voltage high level output voltage low level output voltage high level output voltage low level output voltage v ih (1) v il (1) v ih (2) v il (2) v in (3) v oh (1) v ol (1) v oh (2) v ol (2) v ol (3) v oh (4) v ol (4) v oh (5) v ol (5) i li (1) i li (2) i li (3) i lo 0.7v dd 0.8v dd vss v dd ?0.8 0 v dd ?0.8 0 0 v dd ?0.5 0 v dd ?0.5 0 ?0 ?0 ?0 ? 0.3v dd 0.2v dd v dd v dd 0.4 v dd 0.4 0.4 v dd 0.4 v dd 0.4 10 20 600 5 v v v v v v v v v v v v v v ? ? ? ? conditions min. typ. max. unit applicable pins applicable pins * 1 xtsl, data, xlat, md2, pssl, test, tes2, tes3, dfsw, dirc, sstp, atsk, bcki, lrcki, pcmdi, dts1, dts2, dts7, das0, das1, xwo, pwmi * 2 clok, xrst, exck, sqck, mute, vcki, asye, fsti, sclk, mclk * 3 cltv, fili, rfac, asyi, rfdc, te, se, fe, vc, vctl * 4 mdp, pdo, pco, vpco1, vpco2 * 5 asyo, dout, fsto, c4m, c16m, sbso, sqso, scor, mon, lock, wdck, sens, mds, da01 to da16, lrck, wfck, fok, cout, mirr, dfct, ffon, frdr, fron, ffdr, tfon, trdr, tron, tfdr, sfon, srdr, sron, sfdr, mcko, v16m * 6 fsw * 7 filo * 8 te, se, fe, vc * 9 rfdc * 10 sens, mds, mdp, fsw, pdo, pco, vpco1, vpco2 * 11 rfc * 12 ain1, ain2 * 13 aout1, aout2, lout1, lout2 ?9 CXD2586R/-1 2. ac characteristics (1) xtli pin, vcoi pin (a) when using self-excited oscillation (topr = ?0 to +75?, v dd = av dd = 5.0v 10%) (b) when inputting pulses to xtli and vcoi pins (topr = ?0 to +75?, v dd = av dd = 5.0v 10%) (c) when inputting sine waves to xtli and vcoi pins via a capacitor (topr = ?0 to +75?, v dd = av dd = 5.0v 10%) oscillation frequency f max 7 34 mhz item symbol min. typ. max. unit high level pulse width t whx 13 500 ns low level pulse width t wlx 13 500 ns pulse cycle t cx 26 1000 ns input high level v ihx v dd ?1.0 v input low level v ilx 0.8 v rise time, fall time t r , t f 10 ns item symbol min. typ. max. unit input amplitude v i 2.0 v dd + 0.3 vp-p item symbol min. typ. max. unit t r t f t whx t wlx t cx v ilx v ihx 0.1 v ihx 0.9 v ihx xtli v dd /2 ?10 CXD2586R/-1 (2) clok, data, xlat, sqck, and exck pins (v dd = av dd = 5.0v 10%, v ss = av ss = 0v, topr = ?0 to +75?c) clock frequency clock pulse width setup time hold time delay time latch pulse width exck sqck frequency exck sqck pulse width f ck t wck t su t h t d t wl f t t wt 750 300 300 300 750 750 0.65 0.65 mhz ns ns ns ns ns mhz ns item symbol min. typ. max. unit t wck t wck 1/f ck t h t su t wl t d 1/f t t wt t wt t h t su clok data xlat exck sqck sbso sqso ?11 CXD2586R/-1 (4) cout, mirr and dfct pins operating frequency (v dd = av dd = 5.0v 10%, v ss = av ss = 0v, topr = ?0 to +75?) cout maximum operating frequency mirr maximum operating frequency dfct maximum operating frequency f cout f mirr f dfcth 40 40 5 khz khz khz * 1 * 2 * 3 item symbol min. typ. max. unit conditions * 1 when using a high-speed traverse tzc. * 2 when the rf signal continuously satisfies the following conditions during the above traverse. a = 0.6 to a1.3v = less than 25% * 3 during complete rf signal omission. when settings related to dfct signal generation are typ. (3) sclk pin sclk frequency sclk pulse width delay time f sclk t spw t dls 500 15 1 mhz ns ? item symbol min. typ. max. unit t spw t dls 1/f sclk msb lsb xlat sclk serial read out data (sens) a b b a + b ?12 CXD2586R/-1 (5) bcki, lrcki and pcmdi pins (v dd = 5.0v 10%, topr = ?0 to +75?) input bcki frequency input bcki pulse width input data setup time input data hold time input lrck setup time input lrck hold time t bck t wib t ids t idh t ilrh t ilrs 100 10 15 10 15 4.5 mhz ns item symbol min. typ. max. unit t ilrh t wib t wib t idh t ids t ilrs 50% bcki pcmdi lrcki output voltage (1) output voltage (2) load resistance v out (1) v out (2) r l 0.1v dd * v ss 10 0.9v dd * v dd v v k * 1 * 2 * 1 , * 2 item symbol min. typ. max. unit applicable pins (6) aout1, aout2, lout1 and lout2 pins (v dd = av dd =5.0v 5%, v ss = av ss = 0v, topr = ?0 to +75?) * when a sine wave of 1khz and 0db is output. applicable pins * 1 aout1, aout2 * 2 lout1, lout2 ?13 CXD2586R/-1 dac analog characteristics measurement conditions (ta = 25?, v dd = 5.0v, f s = 44.1khz, signal frequency = 1khz, measurement band = 4hz to 20khz, master clock = 768fs) s/n ratio thd + n dynamic range channel separation output level difference in gain between channels 93 0.01 91 91 1.31 0.1 db % db db v (rms) db item typ. unit (eiaj) * 1 (eiaj) (eiaj) * 1 , * 2 (eiaj) remarks 150p 680p audio analyzer 100k 12k 12k 47 12k shibasoku (am51a) aout1 ain1 lout1 56 57 58 * 1 using "a" weighting filter * 2 ?0db, 1khz input the analog characteristics measurement circuit is shown below. lout1 aout2 ain2 lout2 aout1 ain1 test disk data audio circuit analog 1ch 2ch audio analyzer shibasoku (am51a) 768fs cxd2586 fs = 44.1khz block diagram of analog characteristics measurement lpf external circuit diagram ?14 CXD2586R/-1 contents [1] cpu interface ?-1. cpu interface timing ...................................................................................................................... 15 ?-2. cpu interface command table ...................................................................................................... 15 ?-3. cpu command presets .................................................................................................................. 25 ?-4. description of sens signals ........................................................................................................... 30 [2] subcode interface ?-1. p to w subcode readout ................................................................................................................ 57 ?-2. 80-bit sub q readout ...................................................................................................................... 57 [3] description of modes ?-1. clv-n mode .................................................................................................................................... 63 ?-2. clv-w mode ................................................................................................................................... 63 ?-3. cav-w mode ................................................................................................................................... 63 [4] description of other functions ?-1. channel clock regeneration by the digital pll circuit .................................................................. 65 ?-2. frame sync protection .................................................................................................................... 67 ?-3. error correction ............................................................................................................................... 67 ?-4. da interface ..................................................................................................................................... 68 ?-5. digital out ........................................................................................................................................ 71 ?-6. servo auto sequence ...................................................................................................................... 72 ?-7. digital clv ....................................................................................................................................... 80 ?-8. playback speed ............................................................................................................................... 81 ?-9. dac block playback speed ............................................................................................................ 82 ?-10. dac block input timing .................................................................................................................. 82 ?-11. CXD2586R/-1 clock system ........................................................................................................... 84 [5] description of servo signal processing-system functions and commands ?-1. general description of the servo signal processing system .......................................................... 85 ?-2. digital servo block master clock (mck) ......................................................................................... 86 ?-3. avrg measurement and compensation ........................................................................................ 86 ?-4. e:f balance adjustment function ................................................................................................... 88 ?-5. fcs bias adjustment function ........................................................................................................ 88 ?-6. agcntl function ........................................................................................................................... 90 ?-7. fcs servo and fcs search ........................................................................................................... 92 ?-8. trk and sld servo control ........................................................................................................... 93 ?-9. mirr and dfct signal generation ................................................................................................ 94 ?-10. dfct countermeasure circuit ........................................................................................................ 95 ?-11. anti-shock circuit ............................................................................................................................ 95 ?-12. brake circuit .................................................................................................................................... 96 ?-13. cout signal ................................................................................................................................... 97 ?-14. serial readout circuit ...................................................................................................................... 97 ?-15. writing the coefficient ram ............................................................................................................ 98 ?-16. pwm output .................................................................................................................................... 98 ?-17. dirc input pin ............................................................................................................................... 100 ?-18. servo status changes produced by the lock signal .................................................................. 101 ?-19. description of commands and data sets ..................................................................................... 101 ?-20. list of servo filter coefficients ...................................................................................................... 113 ?-21. filter composition ..................................................................................................................... 115 ?-22. tracking and focus frequency response ............................................................................ 122 [6] application circuit ?-1. application circuit .......................................................................................................................... 123 explanation of abbreviations avrg: average agcntl: automatic gain control fcs: focus trk: tracking sld: sled dfct: defect ?15 CXD2586R/-1 [1] cpu interface ?-1. cpu interface timing cpu interface this interface uses data, clok, and xlat to set the modes. the interface timing chart is shown below. the internal registers are initialized by a reset when xrst = 0. ?-2. cpu interface command table total bit length for each register register 0 to 2 3 4 to 6 7 8 9 a b c to d e 8bit 8 to 24bit 16bit 20bit 24bit 20bit 28bit 20bit 16bit 20bit total bit length 750ns or more d18 d19 d20 d21 d22 d23 750ns or more valid clok data xlat registers ?16 CXD2586R/-1 focus servo on (focus gain normal) focus servo on (focus gain down) focus servo off, 0v out focus servo off, focus search voltage out focus search voltage down focus seach voltage up anti shock on anti shock off brake on brake off tracking gain normal tracking gain up tracking gain up filter select 1 tracking gain up filter select 2 1 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0 1 focus control tracking control register command address d23 to d20 data 1 d19 d18 d17 d16 data 2 d15 d14 d13 d12 data 3 d11 d10 d9 d8 data 4 d7 d6 d5 d4 data 5 d3 d2 d1 d0 command table ($0x to 1x) ? don? care ?17 CXD2586R/-1 tracking servo off tracking servo on forward track jump reverse track jump sled servo off sled servo on forward sled move reverse sled move sled kick level ( 1 basic value) (default) sled kick level ( 2 basic value) sled kick level ( 3 basic value) sled kick level ( 4 basic value) 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 2 3 0 0 1 0 0 0 1 1 tracking mode select command address d23 to d20 register command address d23 to d20 data 1 d19 d18 d17 d16 data 1 d19 d18 d17 d16 data 2 d15 d14 d13 d12 data 2 d15 d14 d13 d12 data 3 d11 d10 d9 d8 data 4 d7 d6 d5 d4 data 5 d3 d2 d1 d0 data 3 d11 d10 d9 d8 data 4 d7 d6 d5 d4 data 5 d3 d2 d1 d0 ? don? care command table ($2x to 3x) register ?18 CXD2586R/-1 kram data (k00) sled input gain kram data (k01) sled low boost filter a-h kram data (k02) sled low boost filter a-l kram data (k03) sled low boost filter b-h kram data (k04) sled low boost filter b-l kram data (k05) sled output gain kram data (k06) focus input gain kram data (k07) sled auto gain kram data (k08) focus high cut filter a kram data (k09) focus high cut filter b kram data (k0a) focus low boost filter a-h kram data (k0b) focus low boost filter a-l kram data (k0c) focus low boost filter b-h kram data (k0d) focus low boost filter b-l kram data (k0e) focus phase compensate filter a kram data (k0f) focus defect hold gain 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 3 0 0 1 1 0 1 0 0 0 0 0 0 select command address 1 d23 to d20 address 2 d19 to d16 address 3 d15 to d12 address 4 d11 d10 d9 d8 data 1 d7 d6 d5 d4 data 2 d3 d2 d1 d0 command table ($340x) register ?19 CXD2586R/-1 kram data (k10) focus phase compensate filter b kram data (k11) focus output gain kram data (k12) anti shock input gain kram data (k13) focus auto gain kram data (k14) hptzc / auto gain high pass filter a kram data (k15) hptzc / auto gain high pass filter b kram data (k16) anti shock high pass filter a kram data (k17) hptzc / auto gain low pass filter b kram data (k18) fix kram data (k19) tracking input gain kram data (k1a) tracking high cut filter a kram data (k1b) tracking high cut filter b kram data (k1c) tracking low boost filter a-h kram data (k1d) tracking low boost filter a-l kram data (k1e) tracking low boost filter b-h kram data (k1f) tracking low boost filter b-l 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 3 0 0 1 1 0 1 0 0 0 0 0 1 select d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 command table ($341x) command address 1 d23 to d20 address 2 d19 to d16 address 3 d15 to d12 address 4 data 1 data 2 register ?20 CXD2586R/-1 kram data (k20) tracking phase compensate filter a kram data (k21) tracking phase compensate filter b kram data (k22) tracking output gain kram data (k23) tracking auto gain kram data (k24) focus gain down high cut filter a kram data (k25) focus gain down high cut filter b kram data (k26) focus gain down low boost filter a-h kram data (k27) focus gain down low boost filter a-l kram data (k28) focus gain down low boost filter b-h kram data (k29) focus gain down low boost filter b-l kram data (k2a) focus gain down phase compensate filter a kram data (k2b) focus gain down defect hold gain kram data (k2c) focus gain down phase compensate filter b kram data (k2d) focus gain down output gain kram data (k2e) not used kram data (k2f) not used 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 3 0 0 1 1 0 1 0 0 0 0 1 0 select d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 command table ($342x) command address 1 d23 to d20 address 2 d19 to d16 address 3 d15 to d12 address 4 data 1 data 2 register ?21 CXD2586R/-1 kram data (k30) fix kram data (k31) anti shock low pass filter b kram data (k32) not used kram data (k33) anti shock high pass filter b-h kram data (k34) anti shock high pass filter b-l kram data (k35) anti shock filter comparate gain kram data (k36) tracking gain up2 high cut filter a kram data (k37) tracking gain up2 high cut filter b kram data (k38) tracking gain up2 low boost filter a-h kram data (k39) tracking gain up2 low boost filter a-l kram data (k3a) tracking gain up2 low boost filter b-h kram data (k3b) tracking gain up2 low boost filter b-l kram data (k3c) tracking gain up phase compensate filter a kram data (k3d) tracking gain up phase compensate filter b kram data (k3e) tracking gain up output gain kram data (k3f) not used 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 3 0 0 1 1 0 1 0 0 0 0 1 1 select d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 command table ($343x) command address 1 d23 to d20 address 2 d19 to d16 address 3 d15 to d12 address 4 data 1 data 2 register ?22 CXD2586R/-1 kram data (k40) tracking hold filter input gain kram data (k41) tracking hold filter a-h kram data (k42) tracking hold filter a-l kram data (k43) tracking hold filter b-h kram data (k44) tracking hold filter b-l kram data (k45) tracking hold filter output gain kram data (k46) not used kram data (k47) not used kram data (k48) focus hold filter input gain kram data (k49) focus hold filter a-h kram data (k4a) focus hold filter a-l kram data (k4b) focus hold filter b-h kram data (k4c) focus hold filter b-l kram data (k4d) focus hold filter output gain kram data (k4e) not used kram data (k4f) not used 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd7 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd6 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd5 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd4 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd3 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd2 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd1 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 kd0 3 0 0 1 1 0 1 0 0 0 1 0 0 select d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 command table ($344x) command address 1 d23 to d20 address 2 d19 to d16 address 3 d15 to d12 address 4 data 1 data 2 register ?23 CXD2586R/-1 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 focus bias limit focus bias data trvsc data focus search speed/ voltage/auto gain dtzc/track jump voltage/auto gain fzsl/sled move/ voltage/auto gain level/auto gain/ dfsw/ (initialize) serial data read mode/select focus bias operation for mirr/ dfct/fok tzc for cout slct hptzc (default) tzc for cout slct dtzc filter others 3 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 fbl9 fb9 tv9 fbl8 fb8 tv8 fbl7 fb7 tv7 fbl6 fb6 tv6 fbl5 fb5 tv5 fbl4 fb4 tv4 fbl3 fb3 tv3 fbl2 fb2 tv2 fbl1 fb1 tv1 tv0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 ft1 0 fzsh vclm dac 0 sfo2 ft0 dtzc fzsl vclc sd6 fbon sfo1 fs5 tj5 sm5 flm sd5 fbss sdf2 fs4 tj4 sm4 flc0 sd4 fbup sdf1 fs3 tj3 sm3 rflm sd3 fbv1 max2 fs2 tj2 sm2 rflc sd2 fbv0 max1 fs1 tj1 sm1 agf sd1 0 sfox fs0 tj0 sm0 agt sd0 tjd0 btf ftz sfjp ags dfsw 0 fps1 d2v2 fg6 tg6 agj lksw 0 fps0 d2v1 fg5 tg5 aggf tblm 0 tps1 d1v2 fg4 tg4 aggt tclm 0 tps0 d1v1 fg3 tg3 agv1 flc1 0 ceit rint fg2 tg2 agv2 tlc2 0 sjhd 0 fg1 tg1 aghs tlc1 0 inbk 0 fg0 tg0 aght tlc0 0 mti0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 f1nm 0 f1dm agg4 f3nm xt4d f3dm xt2d t1nm 0 t1um drr2 t3nm drr1 t3um drr0 dfis 0 tlcd asfg rflp 0 0 lpas 0 sro1 0 sro0 miri aghf xt1d cot2 1 1 0 0 0 1 0 0 1 1 select register command address 1 d23 to d20 d19 d18 d17 d16 address 2 d15 d14 d13 d12 data 1 d11 d10 d9 d8 data 2 d7 d6 d5 d4 data 3 d3 d2 d1 d0 address d23 to d20 d19 d18 d17 d16 data 1 d15 d14 d13 d12 data 2 d11 d10 d9 d8 data 3 d7 d6 d5 d4 data 4 d3 d2 d1 d0 address d23 to d20 d19 d18 d17 d16 data 1 d15 d14 d13 d12 data 2 d11 d10 d9 d8 data 3 d7 d6 d5 d4 data 4 d3 d2 d1 d0 address d23 to d20 d19 d18 d17 d16 data 1 d15 d14 d13 d12 data 2 d11 d10 d9 d8 data 3 d7 d6 d5 d4 data 4 d3 d2 d1 d0 command table ($34fx to 3fx) ? don? care ?24 CXD2586R/-1 auto sequence blind (a, e), overflow (c, g), brake (b) sled kick, kick (f), brake (d) auto sequence (n) track jump count setting mode setting function specification audio ctrl traverse monitor counter setting spindle servo coefficient setting clv ctrl spd mode 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 as3 tr3 sd3 32768 cd- rom dclv on/off 0 32768 gain mdp1 dclv pwm md cm3 as2 tr2 sd2 16384 dout mute dspb on/off 0 16384 gain mdp0 tb cm2 as1 tr1 sd1 8192 dout mute-f aseq on/off mute 8192 gain mds1 tp cm1 as0 tr0 sd0 4096 wsel dpll on/off att 4096 gain mds0 clvs gain cm0 mt3 0 kf3 2048 vco sel biligl main pct1 2048 gain dclv1 vp7 epwm mt2 0 kf2 1024 ashs biligl sub pct2 1024 gain dclv0 vp6 spdc mt1 0 kf1 512 soct flfc dads 512 0 vp5 icap mt0 0 kf0 256 vco sel2 0 soc2 256 0 vp4 sfsl lssl 0 0 128 ksl3 dac emp at1d7 128 0 vp3 vc2c 0 0 0 64 ksl2 dac att at1d6 64 0 vp2 hifc 0 0 0 32 ksl1 0 at1d5 32 0 vp1 lpwr 0 0 0 16 ksl0 0 at1d4 16 0 vp0 vpon 8 0 plm3 at1d3 8 gain cav1 4 0 plm2 at1d2 4 gain cav0 2 1 plm1 at1d1 2 fcsw 1 0 plm0 at1d0 1 0 4 5 6 7 8 9 a b c d e command address d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 1 data 2 data 3 data 4 command table ($4x to ex) ? don? care audio ctrl 1 0 1 0 at2d7 at2d6 at2d5 at2d4 at2d3 at2d2 at2d1 at2d0 a command address data 1 data 2 data 3 data 4 d3 d2 d1 d0 d3 d2 d1 d0 data 5 data 6 register register ?25 CXD2586R/-1 focus servo off, 0v out tracking gain up filter select 1 tracking servo off sled servo off sled kick level ( 1 + basic value) (default) kram data ($3400xx to $344fxx) 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 0 0 0 0 0 0 1 0 0 1 0 focus control tracking control tracking mode command address d23 to d20 data 1 d19 d18 d17 d16 data 2 d15 d14 d13 d12 data 3 d11 d10 d9 d8 data 4 d7 d6 d5 d4 data 5 d3 d2 d1 d0 command 3 select address d23 to d20 0 0 1 1 0 0 1 1 0 1 0 0 0 see the coefficient preset values table. 0 0 0 0 data 1 d19 d18 d17 d16 data 2 d15 d14 d13 d12 data 3 d11 d10 d9 d8 data 4 d7 d6 d5 d4 data 5 d3 d2 d0 d0 address 1 d23 to d20 d19 d18 d17 d16 address 2 d15 d14 d13 d12 address 3 d11 d10 d9 d8 data 1 d7 d6 d5 d4 data 2 d3 d2 d0 d0 ?-3. cpu command presets command preset table ($0x to 34x) ? don? care register register ?26 CXD2586R/-1 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 focus bias limit focus bias data trvsc data focus search speed/ voltage auto gain dtzc/track jump voltage auto gain fzsl/sled move/ voltage/auto gain level/auto gain/ dfsw/ (initialize) serial data read mode/select focus bias operation for mirr/ dfct/fok tzc for cout slct hptzc (default) filter others 3 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 select command address 1 d23 to d20 d19 d18 d17 d16 address 2 d15 d14 d13 d12 data 1 d11 d10 d9 d8 data 2 d7 d6 d5 d4 data 3 d3 d2 d1 d0 address d23 to d20 d19 d18 d17 d16 data 1 d15 d14 d13 d12 data 2 d11 d10 d9 d8 data 3 d7 d6 d5 d4 data 4 d3 d2 d1 d0 address d23 to d20 d19 d18 d17 d16 data 1 d15 d14 d13 d12 data 2 d11 d10 d9 d8 data 3 d7 d6 d5 d4 data 4 d3 d2 d1 d0 address d23 to d20 d19 d18 d17 d16 data 1 d15 d14 d13 d12 data 2 d11 d10 d9 d8 data 3 d7 d6 d5 d4 data 4 d3 d2 d1 d0 command preset table ($34fx to 3fx) ? don? care register ?27 CXD2586R/-1 auto sequence blind (a, e), brake (b), overflow (c, g) sled kick, brake (d), kick (f) auto sequence (n) track jump count setting mode setting function specification audio ctrl traverse monitor counter setting spindle servo coefficient setting clv ctrl spd mode 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 4 5 6 7 8 9 a b c d e register command address d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 1 data 2 data 3 data 4 command preset table ($4x to ex) ? don? care audio ctrl 1 0 1 0 1 1 1 1 1 1 1 1 a register command address data 1 data 2 data 3 data 4 d3 d2 d1 d0 d3 d2 d1 d0 data 5 data 6 ?28 CXD2586R/-1 ?29 CXD2586R/-1 ?30 CXD2586R/-1 ?-4. description of sens signals sens output microcomputer serial register (latching not required) $0x $1x $2x $38 $38 $30 to 37 $3a $3b to 3f $3904 $3908 $390c $391c $391d $391f $4x $5x $6x $ax $bx $cx $ex $7x, 8x, 9x, dx, fx z z z z z z z z z z z z z z z z z gfs comp cout ov64 z fzc as tzc agok * xavebsy * sstp fbias count stop sstp te avrg reg. fe avrg reg. vc avrg reg. trvsc reg. fb reg. rfdc avrg reg. xbusy fok 0 gfs comp cout ov64 0 9 bit 9 bit 9 bit 9 bit 9 bit 8 bit aseq = 0 aseq = 1 output data length * $38 outputs agok during agt and agf command settings, and xavebsy during avrg measurement. sstp is output in all other cases. ?31 CXD2586R/-1 description of sens signals the sens pin is high impedance. low while the auto sequencer is in operation, high when operation terminates. outputs the same signal as the fok pin. high for "focus ok". high when the regenerated frame sync is obtained with the correct timing. counts the number of tracks set with reg b. high when reg b is latched, low when the initial reg b number is input by cnin. counts the number of tracks set with reg b. high when reg b is latched, toggles each time the reg b number is input by cnin. while $44 and $45 are being executed, toggles with each cnin 8-count instead of the reg b number. low when the efm signal is lengthened by 64 channel clock pulses or more after passing through the sync detection filter. z xbusy fok gfs comp cout ov64 sens output ?32 CXD2586R/-1 the meaning of the data for each address is explained below. $4x commands register name 4 data 1 command data 2 max timer value data 3 timer range as3 as2 as1 as0 mt3 mt2 mt1 mt0 lssl 0 0 0 command cancel fine search focus-on 1 track jump 10 track jump 2n track jump m track move 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 rxf 1 rxf rxf rxf rxf as3 as2 as1 as0 rxf = 0 forward rxf = 1 reverse when the focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted. when the track jump commands ($44 to $45, $48 to $4d) are canceled, $25 is sent and the auto sequence is interrupted. to disable the max timer, set the max timer value to 0. $5x commands max timer value mt3 23.2ms 1.49s 11.6ms 0.74s 5.8ms 0.37s 2.9ms 0.18s 0 1 0 0 0 0 0 0 mt2 mt1 mt0 lssl 0 0 0 timer range timer tr3 tr2 tr1 tr0 blind (a, e), overflow (c, g) brake (b) 0.18ms 0.36ms 0.09ms 0.18ms 0.045ms 0.09ms 0.022ms 0.045ms ?33 CXD2586R/-1 command data 1 data 2 data 3 data 4 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 auto sequence track jump count setting this command is to set n when a 2n track jump is executed, to set m when an m track move is executed and to set the jump count when fine search is executed for auto sequence. the maximum track count is 65,535, but note that with a 2n-track jump the maximum track jump count depends on the mechanical limitations of the optical system. when the track jump count is from 0 to 15, the cout signal is used to count tracks for 2n-track jump/m track move; when the count is 16 or over, the mirr signal is used. for fine search, the cout signal is used to count tracks. $7x commands auto sequence track jump count setting $6x commands register name 6 data 1 kick (d) data 2 kick (f) sd3 sd2 sd1 sd0 kf3 kf2 kf1 kf0 timer sd3 sd2 sd1 sd0 when executing kick (d) $44 or $45 when executing kick (d) $4c or $4d 23.2ms 11.6ms 11.6ms 5.8ms 5.8ms 2.9ms 2.9ms 1.45ms timer kf3 kf2 kf1 kf0 kick (f) 0.72ms 0.36ms 0.18ms 0.09ms ?34 CXD2586R/-1 * see mute conditions (1), (2), and (4) to (6) under $ax commands for other mute conditions. md2 other mute conditions * dout mute d.out mute f dout output off 0db db da output 0db 0db db 0db db db 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 command data 1 mode specification cd- rom dout mute dout mute-f wsel d3 d2 d1 d0 data 2 vco sel1 ashs soct vco sel2 d3 d2 d1 d0 data 3 ksl3 ksl2 ksl1 ksl0 d3 d2 d1 d0 $8x commands command bit dout mute = 1 dout mute = 0 when digital out is on (md2 pin = 1), dout output is muted. when digital out is on, dout output is not muted. processing command bit d. out mute f = 1 d. out mute f = 0 when digital out is on (md2 pin = 1), da output is muted. da output mute is not affected when digital out is either on or off. processing command bit cdrom = 1 cdrom = 0 c2po timing see the timing chart 1-3 see the timing chart 1-3 cdrom mode; average value interpolation and pre-value hold are not performed. audio mode; average value interpolation and pre-value hold are performed. processing ?35 CXD2586R/-1 command bit sync protection window width wsel = 1 wsel = 0 26 channel clock * * 6 channel clock anti-rolling is enhanced. sync window protection is enhanced. application * in normal-speed playback, channel clock = 4.3218mhz. command bit function ashs = 0 ashs = 1 the command transfer rate to ssp is set to normal speed. the command transfer rate to ssp is set to half speed. command bit function soct = 0 soct = 1 sub q is output from the sqso pin. each output signal is output from the sqso pin. input the readout clock to sqck. (see the timing chart 2-4.) command bit vcosel1 ksl3 ksl2 processing multiplier pll vco1 is set to normal speed, and the output is 1/1 frequency-divided. multiplier pll vco1 is set to normal speed, and the output is 1/2 frequency-divided. multiplier pll vco1 is set to normal speed, and the output is 1/4 frequency-divided. multiplier pll vco1 is set to normal speed, and the output is 1/8 frequency-divided. multiplier pll vco1 is set to high speed * , and the output is 1/1 frequency-divided. multiplier pll vco1 is set to high speed * , and the output is 1/2 frequency-divided. multiplier pll vco1 is set to high speed * , and the output is 1/4 frequency-divided. multiplier pll vco1 is set to high speed * , and the output is 1/8 frequency-divided. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 * approximately twice the normal speed command bit vcosel2 ksl1 ksl0 processing wide-band pll vco2 is set to normal speed, and the output is 1/1 frequency-divided. wide-band pll vco2 is set to normal speed, and the output is 1/2 frequency-divided. wide-band pll vco2 is set to normal speed, and the output is 1/4 frequency-divided. wide-band pll vco2 is set to normal speed, and the output is 1/8 frequency-divided. wide-band pll vco2 is set to high speed * , and the output is 1/1 frequency-divided. wide-band pll vco2 is set to high speed * , and the output is 1/2 frequency-divided. wide-band pll vco2 is set to high speed * , and the output is 1/4 frequency-divided. wide-band pll vco2 is set to high speed * , and the output is 1/8 frequency-divided. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 * approximately twice the normal speed * see "?-8. playback speed" for settings. ?36 CXD2586R/-1 command data 1 function specifications dclv on-off dspb on-off a.seq on-off d.pll on-off d3 d2 d1 d0 data 2 biligl main biligl sub flfc d3 d2 d1 0 d0 $9x commands command bit dclv on/off = 0 in clvs mode fsw = low, mon = high, mds = z; mdp = servo control signal, carrier frequency of 230hz at tb = 0, and 460hz at tb = 1. fsw = z, mon = high; mds = speed control signal, carrier frequency of 7.35khz; mdp = phase control signal, carrier frequency of 1.8khz. when dclv pwm and md = 1 (prohibited in clv- w and cav-w modes) mds = pwm polarity signal, carrier frequency of 132khz. mdp = pwm absolute value output (binary), carrier frequency of 132khz. when dclv pwm and md = 0 mds = z mdp = ternary pwm output, carrier frequency of 132khz. in clvp mode in clvs and clvp modes dclv on/off = 1 (fsw, mon not required) clv mode contents when dclv on/off = 1 for the digital clv servo, the sampling frequency of the internal digital filter switches simultaneously with the clvp/clvs switching. therefore, the cut-off frequency for the clvs is fc = 70hz when t b = 0, and fc = 140hz when t b = 1. command bit dspb = 0 dspb = 1 normal-speed playback, c2 error correction quadruple correction. double-speed playback, c2 error correction double correction. processing flfc is normally 0. flfc is 1 in cav-w mode, for any playback speed. ?37 CXD2586R/-1 command bit dpll = 0 * dpll = 1 rfpll is analog. pdo, vcoi and vcoo are used. rfpll is digital. pdo is high impedance. meaning command bit biligl sub = 0 biligl sub = 1 stereo sub main mute biligl main = 0 biligl main = 1 definition of bilingual capable main, sub and stereo: the left channel input is output to the left and right channels for main. the right channel input is output to the left and right channels for sub. the left and right channel inputs are output to the left and right channels for stereo. * external parts for the fili, filo, pco pins are required even when analog pll is selected. command data 3 function specifications dac emph dac att 00 d11 d10 d9 d8 data 4 plm3 plm2 plm1 d7 d6 d5 plm0 d4 the command bits control the dac. note) for normal stereo, channel 1 is the left channel and channel 2 is the right channel. command bit dac emph = 1 dac emph = 0 applies digital de-emphasis. when fs = 44.1khz, the emphasis constants are t 1 = 50 s and t 2 = 15 s. turns digital de-emphasis off. processing command bit dac att = 1 dac att = 0 identical digital attenuation control is used for both channels 1 and 2. when common attenuation data is specified, the attenuation values for channel 1 is used. independent digital attenuation control is used for both channels 1 and 2. processing dac play mode command dac play mode plm3 plm2 plm1 plm0 d7 d6 d5 d4 by controlling these command bits, the dac outputs channel 1 and channel 2 can be output in 16 different combinations of left channel, right channel, left + right channel, and mute. the relationship between the commands and the outputs is shown on the table on the following page. ?38 CXD2586R/-1 plm3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 mute l r l + r mute l r l + r mute l r l + r mute l r l + r mute mute mute mute l l l l r r r r l + r l + r l + r l + r mute reverse stereo mono plm2 plm1 plm0 channel 1 output channel 2 output remarks note) for normal stereo, channel 1 is the left channel and channel 2 is the right channel. the output data of l+r is (l+r)/2 to prevent overflow. ?39 CXD2586R/-1 command data 1 audio ctrl 0 0 mute att d3 d2 d1 d0 data 2 pct1 pct2 d3 d2 dads soc2 d1 d0 $ax commands command bit mute = 0 mute = 1 mute off if other mute conditions are not set. mute on. peak register reset. meaning command bit att = 0 att = 1 attenuation off ?2db meaning mute conditions (1) when register a mute = 1. (2) when mute pin = 1. (3) when register 8 d.out mute f = 1 and the digital out is on (md2 pin =1). (4) when gfs stays low for over 35ms (during normal-speed). (5) when register 9 biligl main = sub =1. (6) when register a pct1 = 1 and pct2 = 0. (1) to (4) perform zero-cross muting with a 1 ms time limit. command bit pct1 0 0 1 1 pct2 0 1 0 1 normal mode level meter mode peak meter mode normal mode 0db 0db mute 0db c1: double; c2: quadruple c1: double; c2: quadruple c1: double; c2: double c1: double; c2: double meaning pcm gain ecc error correction ability description of level meter mode (see the timing chart 1-4.) when the lsi is set to this mode, it performs digital level meter functions. when the 96-bit clock is input to sqck, 96 bits of data are output to sqso. the initial 80 bits are sub q data. (see ?. subcode interface.) the last 16 bits are lsb first, which are 15-bit pcm data (absolute values) and l/r flag. l/r flag is high when the 15-bit pcm data is from the left channel and low from the right channel. pcm data is reset zero and the l/r flag is reversed after one readout. then level measuring continues until the next readout. ?40 CXD2586R/-1 description of peak meter mode (see the timing chart 1-5.) when the lsi is set to this mode, the maximum pcm data value is detected regardless of if it comes from the left or right channel. the 96-bit clock must be input to sqck to read out this data. when the 96-bit clock is input, 96 bits of data are output to sqso and the lsi internal register is set the value again. in other words, the pcm maximum value detection register is not reset to zero by the readout. to reset the pcm maximum value register to zero, set pct1 = pct2 = 0 or set the $ax mute. the sub q absolute time is automatically controlled in this mode. in other words, after the maximum value is generated, the absolute time for crc to become ok is retained in the memory. normal operation is conducted for the relative time. the final bit (l/r flag) of the 96-bit data is normally 0. the pre-value hold and average value interpolation data are fixed to level (? ) in this mode. sens output switching this enables the sqso pin signal to be output from the sens pin. when soc2 = 0, sens output is performed as usual. when soc2 = 1, the sqso pin signal is output from the sens pin. at this time, the readout clock is input to the sclk pin. note) soc2 should be switched when sqck = sclk = high. command bit dads = 0 dads = 1 set to 0 when crystal = 33.8688mhz. set to 1 when crystal = 16.9344mhz. processing command bit soc2 = 0 soc2 = 1 the sens signal is output from the sens pin as usual. the sqso pin signal is output from the sens pin. processing ?41 CXD2586R/-1 dac digital attenuator command data 3 d3 at1d7 at1d6 at1d5 at1d4 at1d3 at1d2 at1d1 at1d0 at2d7 at2d6 at2d5 at2d4 at2d3 at2d2 at2d1 at2d0 audio ctrl d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 4 data 5 data 6 note) at1d7 to at1d0 are the channel 1 att control bits. at2d7 to at2d0 are the channel 2 att control bits. command bits at1d7 to at1d0 (at2d7 to at2d0) ff (h) fe (h) 01 (h) 00 (h) 0db ?.034db ?8.131db ? audio output the attenuation data consists of 8 bits each for channels 1 and 2; the dac att bit can be used to control channels 1 and 2 with common attenuation data. (when common attenuation data is specified, the attenuation values for channel 1 is used.) an attenuation value, from 00(h) to ff(h), is determined according to the following expression: att = 20 log [input data/255] db example: when the attenuation data is fa(h): att = 20 log [250/255] db = ?.172db soft mute with the soft mute function, when the attenuation data goes from ff(h) to 00(h) and vice versa, muting is turned on and off over the muting time of 1024fs [s] = 23.2 [ms] (fs = 44.1khz). attenuation assume the attenuation data att1, att2, and att3, where att1 > att3 > att2. first, assume att1 is transferred and then att2 is transferred. if att2 is transferred before att1 is reached (state "a" in the diagram), then the value continues approaching att2. next, if att3 is transferred before att2 is reached (state "b" or "c" in the diagram), the attenuation begins approaching att3 from the current point. note that it takes 1024/fs [s] (fs = 44.1khz for cd players) to transit between attenuation data (from 0db to ? ). att1 a b c att2 0db att3 handling of the attenuation value ?42 CXD2586R/-1 i/o sync circuit related pins: lrck and xwo during normal operation, the i/o sync circuit automatically synchronizes with the input lrck, and its operation proceeds in phase with the serial input data. however, there is a chance that synchronization will not be performed if there is a great deal of jitter in lrck, if the power has just been turned on, etc. in this case, forced synchronization is possible by setting xwo low for 2/fs or more. the forced synchronization operation is performed at the second rising edge of lrck after the xwo pin is set low. $bx commands this command sets the traverse monitor count. command data 1 data 2 data 3 data 4 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 traverse monitor count setting when the set number of tracks are counted during fine search, the sled control for the traverse cycle control goes off. the traverse monitor count is set to monitor the traverse status from the sens output as comp and cout. ?43 CXD2586R/-1 servo coefficient setting clv ctrl ($dx) gain mdp1 gain mdp0 gain mds1 gain mds0 gain clvs gain mds1 0 0 0 0 1 1 gain mds0 0 0 1 1 0 0 gain clvs 0 1 0 1 0 1 gclvs ?2db ?db ?db 0db 0db +6db command d3 data 1 d2 d1 d0 gain dclv0 gain dclv1 0 0 d3 data 2 explanation valid only when dclv = 1. valid when dclv = 1 or 0. d2 d1 d0 $cx commands the spindle servo gain is externally set when dclv = 1. clvs mode gain setting: gclvs note) when dclv = 0, the clvs gain is as follows. when gain clvs = 0, gclvs = ?2db. when gain clvs = 1, gclvs = 0db. gain mdp1 0 0 1 gain mdp0 0 1 0 gmdp ?db 0db +6db gain dclv1 0 0 1 gain dclv0 0 1 0 gdclv 0db +6db +12db gain mds1 0 0 1 gain mds0 0 1 0 gmds ?db 0db +6db clvp mode gain setting: gmdp, gmds dclv overall gain setting: gdclv ?44 CXD2586R/-1 $dx commands see the $cx commands. command bit dclv pwm md = 1 dclv pwm md = 0 digital clv pwm mode specified. both mds and mdp are used. clv-w and cav-w modes can not be used. digital clv pwm mode specified. ternary mdp values are output. clv-w and cav-w modes can be used. explanation command bit tb = 0 tb = 1 tp = 0 tp = 1 bottom hold at a cycle of rfck/32 in clvs and clvh modes. bottom hold at a cycle of rfck/16 in clvs and clvh modes. peak hold at a cycle of rfck/4 in clvs mode. peak hold at a cycle of rfck/2 in clvs mode. explanation command data 1 clv ctrl dclv pwm md tb tp gain clvs d3 d2 d1 d0 data 2 vp7 vp6 vp5 vp4 d3 d2 d1 d0 data 3 vp3 vp2 vp1 vp0 d3 d2 d1 d0 the rotational velocity r of the spindle can be expressed with the following equation. r = r: relative velocity at normal speed = 1 n: vp0 to 7 setting value 256 ?n 32 command bit vp0 to 7 = f0 (h) : vp0 to 7 = e0 (h) : vp0 to 7 = c0 (h) : vp0 to 7 = a0 (h) playback at half (normal) speed to playback at normal (double) speed to playback at double (quadruple) speed to playback at (sextuple) speed description note) 1. values when mclk is 16.9344mhz and xtsl is low or when mclk is 33.8688mhz and xtsl is high. 2. values in parentheses are for when dspb is 1. for the CXD2586R f0 e0 d0 c0 1 2 3 4 r ?relative velocity [times] vp0 to 7 setting value [hex] dspb = 1 dspb = 0 b0 a0 5 6 ?45 CXD2586R/-1 command bit vp0 to 7 = f0 (h) : vp0 to 7 = e0 (h) : vp0 to 7 = c0 (h) : vp0 to 7 = a0 (h) : vp0 to 7 = 80 (h) playback at half (normal) speed to playback at normal (double) speed to playback at double (quadruple) speed to playback at triple (sextuple) speed to playback at (octuple) speed description note) 1. values when mclk is 16.9344mhz and xtsl is low or when mclk is 33.8688mhz and xtsl is high. 2. values in parentheses are for when dspb is 1. for the CXD2586R-1 6 7 f0 e0 d0 c0 1 2 3 4 r ?relative velocity [times] vp0 to 7 setting value [hex] dspb = 1 dspb = 0 b0 a0 5 8 90 80 ?46 CXD2586R/-1 $ex commands command data 1 spd mode cm3 cm2 cm1 cm0 d3 d2 d1 d0 data 2 epwm spdc icap sfsl d3 d2 d1 d0 data 3 vc2c hifc lpwr vpon d3 d2 d1 d0 command bit cm3 cm2 cm1 explanation spindle stop mode. * spindle forward rotation mode. * spindle reverse rotation mode. valid only when lpwr=0, in any modes. * rough servo mode. when the rf-pll circuit isn't locked, this mode is used to pull the disc rotations within the rf- pll capture range. pll servo mode. automatic clvs/clvp switching mode. used for normal playback. 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 1 1 cm0 0 0 0 0 1 0 mode stop kick brake clvs clvp clva * see the timing charts 1-6 to 1-12. command bit epwm spdc icap explanation crystal reference clv servo. used for playback in clv-w mode. * spindle control with vp0 to 7. spindle control with the external pwm. 0 0 0 1 0 0 1 0 0 0 1 1 sfsl 0 0 0 0 vc2c 0 1 0 0 hifc 0 1 1 1 lpwr 0 0 0 0 vpon 0 0 1 1 mode clv-n clv-w cav-w cav-w * figs. 3-1 and 3-2 show the control flow with the microcomputer software in clv-w mode. ?47 CXD2586R/-1 mode dclv dclv pwm md lpwr command timing chart clv-n clv-w cav-w 0 1 1 1 0 0 1 0 0 0 0 0 0 1 0 1 kick brake stop kick brake stop kick brake stop kick brake stop kick brake stop kick brake stop kick brake stop 1-6 (a) 1-6 (b) 1-6 (c) 1-7 (a) 1-7 (b) 1-7 (c) 1-8 (a) 1-8 (b) 1-8 (c) 1-9 (a) 1-9 (b) 1-9 (c) 1-10 (a) 1-10 (b) 1-10 (c) 1-11 (a) 1-11 (b) 1-11 (c) 1-12 (a) 1-12 (b) 1-12 (c) mode dclv dclv pwm md lpwr timing chart clv-n clv-w cav-w 1 1 1 0 1 0 0 0 0 0 1 0 1 0 1 1-13 1-14 1-15 1-16 1-17 (cav = 0) 1-18 (cav = 0) 1-19 (cav = 1) 1-20 (cav = 1) note) the clv-w and cav-w modes support control only by the ternary output of the mdp pin. therefore, set dclv to 1 and dclv pwm md to 0 in clv-w and cav-w modes. ?48 CXD2586R/-1 command bit fcsw = 0 fcsw = 1 the vpco2 pin is not used and it is hi-z. the vpco2 pin is used and the pin signal is the same as vpco1. processing command spd mode data 4 this sets the gain when controlling the spindle with the phase comparator in cav-w mode. d3 d2 d1 d0 gain cav1 gain cav0 fcsw 0 gain cav1 0 0 1 1 gain cav0 0 1 0 1 gain 0db ?db ?2db ?8db ?49 CXD2586R/-1 timing chart 1-3 rch 16bit c2 pointer lch 16bit c2 pointer if c2 pointer = 1, data is ng c2 pointer for upper 8bits c2 pointer for lower 8bits rch c2 pointer c2 pointer for upper 8bits c2 pointer for lower 8bits lch c2 pointer lrck wdck cdrom = 0 c2po cdrom=1 c2po 48 bit slot ?50 CXD2586R/-1 timing chart 1-4 level meter timing 96 clock pulses wfck 123 96 clock pulses crcf crcf 123 peak data of this section 16 bit r/l l/r 96 bit data hold section 123 8081 96 crcf sqck d0 d1 d2 d3 d4 d5 d6 d13 d14 l/r peak data l/r flag sub q data see "sub code interface" 15-bit peak-data absolute value display, lsb first 750ns to 120 s sqck sqso sqso ?51 CXD2586R/-1 timing chart 1-5 measurement peak meter timing 96 clock pulses crcf wfck 123 measurement measurement 96 clock pulses crcf crcf 123 sqck ?52 CXD2586R/-1 timing chart 1-6 clv-n mode dclv = dclv pwm md = lpwr = 0 z kick mds mdp h fsw l mon h (a) kick z brake mds mdp fsw l mon h (b) brake z stop mds mdp fsw l mon (c) stop l l l timing chart 1-7 clv-n mode dclv = 1, dclv pwm md = lpwr = 0 z kick mds mdp h fsw l mon h (a) kick z brake mds mdp fsw l mon h (b) brake z stop mds mdp fsw l mon (c) stop z l z l z ?53 CXD2586R/-1 timing chart 1-8 clv-n mode dclv = dclv pwm md = 1, lpwr = 0 kick mds mdp h fsw l mon h (a) kick brake mds mdp fsw l mon h (b) brake stop mds mdp fsw l mon (c) stop l l h l l l h timing chart 1-9 clv-w mode (when following the spindle rotational velocity) dclv = 1, dclv pwm md = lpwr = 0 z kick mds mdp h fsw l mon h (a) kick z brake mds mdp fsw l mon h (b) brake z stop mds mdp fsw l mon (c) stop z l z other than when following the velocity, the timing is the same as timing chart 1-6 (a). l z other than when following the velocity, the timing is the same as timing chart 1-6 (b). ?54 CXD2586R/-1 timing chart 1-10 clv-w mode (when following the spindle rotational velocity) dclv = 1, dclv pwm md = 0, lpwr = 1 z kick mds mdp h fsw l mon h (a) kick z brake mds mdp fsw l mon h (b) brake z z stop mds mdp fsw l mon (c) stop z l z other than when following the velocity, the timing is the same as timing chart 1-6 (a). timing chart 1-11 cav-w mode dclv = 1, dclv pwm md = lpwr = 0 z kick mds mdp h fsw l mon h (a) kick z brake mds mdp fsw l mon h (b) brake z stop mds mdp fsw l mon (c) stop z l h ?55 CXD2586R/-1 timing chart 1-12 cav-w mode dclv = 1, dclv pwm md = 0, lpwr = 1 z kick mds mdp h fsw l mon h (a) kick z brake mds mdp fsw l mon h (b) brake z z stop mds mdp fsw l mon (c) stop z h timing chart 1-13 clv-n mode dclv pwm md = lpwr = 0 z mds mdp acceleration z deceleration 132khz 7.6 s n ?236 (ns) n = 0 to 31 timing chart 1-14 clv-n mode dclv pwm md = 1, lpwr = 0 mds mdp acceleration deceleration 132khz 7.6 s n ?236 (ns) n = 0 to 31 output waveforms with dclv = 1 ?56 CXD2586R/-1 timing chart 1-15 clv-w mode dclv pwm md = lpwr = 0 z mds mdp acceleration z deceleration 264khz 3.8 s output waveforms with dclv = 1 timing chart 1-16 clv-w mode dclv pwm md = 0, lpwr = 1 z mds mdp acceleration z 264khz 3.8 s output waveforms with dclv = 1 the brake pulse is masked when lpwr = 1. timing chart 1-17 cav-w mode epwm = dclv pwm md = lpwr = 0 mdp acceleration z deceleration 264khz 3.8 s timing chart 1-18 cav-w mode epwm = 1, dclv pwm md = 0, lpwr = 1 mdp acceleration z 264khz 3.8 s the brake pulse is masked when lpwr = 1. ?57 CXD2586R/-1 timing chart 1-19 cav-w mode epwm = 1, dclv pwm md = lpwr = 0 pwmi mdp h l h l acceleration deceleration timing chart 1-20 cav-w mode epwm = 1, dclv pwm md = 0, lpwr = 1 pwmi mdp h l h z acceleration the brake pulse is masked when lpwr = 1. note) the clv-w and cav-w modes support control only by the ternary output of the mdp pin. therefore, set dclv pwm md to 0 in clv-w and cav-w modes. ?58 CXD2586R/-1 ?. subcode interface there are two methods for reading out a subcode externally. the 8-bit subcodes p to w can be read from sbso by inputting exck. sub q can be read out after checking crc of the 80 bits in the subcode frame. sub q can be read out from the sqso pin by inputting 80 clock pulses to sqck pin when scor comes correctly and crcf is high. ?-1. p to w subcode readout data can be read out by inputting exck immediately after wfck falls. (see the timing chart 2-1.) ?-2. 80-bit sub q readout fig. 2-2 shows the peripheral block of the 80-bit sub q register. first, sub q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the crc check circuit. 96-bit sub q has been inputted, and if the crc is ok, it is output to sqso with crcf = 1. in addition, the 80 bits are loaded into the parallel/serial register. when sqso goes high after scor is output, the cpu determines that new data (which passed the crc check) has been loaded. in the CXD2586R/-1, when 80-bit data is loaded, the order of the msb and lsb is inverted within each byte. as a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered lsb first. once the 80-bit data load is confirmed, sqck is input so that the data can be read. the sqso input is detected, and the retriggerable monostable multivibrator for low is reset. the retriggerable monostable multivibrator has a time constant from 270 to 400 s. when the duration when sqck is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the s/p register is not loaded into the p/s register. while the monostable multivibrator is being reset, data cannot be loaded in the peak detection parallel/serial register or the 80-bit parallel/serial register. in other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by crcok and others. in this lsi, the previously mentioned peak detection register can be connected to the shift-in of the 80-bit p/s register. input for ring control 1 is connected to the output of it in peak meter or level meter mode. same goes for ring 2 in peak meter mode. this is because the register is reset with each readout in level meter mode, and to prevent readout destruction in peak meter mode. as a result , the 96-bit clock must be input in peak meter mode. the absolute time after peak is stored in the memory in peak meter mode. (see the timing chart 2-3.) the high and low intervals for sqck should be between 750ns and 120 s. ?59 CXD2586R/-1 timing chart 2-1 internal pll clock 4.3218 d mhz wfck scor exck sbso 750ns max s0 ?s1 q r wfck scor exck sbso s0?1 q r s t u v w s0?1 p1 q r s t u v w p1 p2 p3 same same subcode p.q.r.s.t.u.v.w read timing ?60 CXD2586R/-1 block diagram 2-2 8 8 8 8 8 8 8 8 8 order inversion 16 peak detection load control ring control 2 crcf mix monostable multivibrator crcc abs time load control for peak value 16 bit p/s register ring control 1 so si sqso sqck shift shift subq ld ld ld ld ld ld ld ld so hg f ed c b a abcde fgh si 80 bit p/s register 80 bit s/p register (afram) (asec) (amin) addrs ctrl sin subq ?61 CXD2586R/-1 timing chart 2-3 1 2 3 91 92 93 94 95 96 97 98 wfck scor sqso sqck monostable multivibrator (internal) crcf1 determined by mode crcf2 80 or 96 clock register load forbidder 270 to 400 s when sqck = high. 750ns to 120 s 300ns max crcf adr0 adr1 adr2 adr3 ctl0 ctl1 ctl2 ctl3 sqck sqso 1 2 3 crcf1 ?62 CXD2586R/-1 timing chart 2-4 example: $8020 latch set sqck high during this interval. internal signal latch per0 per1 per2 per3 per4 per5 per6 per7 c1f0 c1f1 c1f2 c2f0 c2f1 c2f2 fok gfs lock emph 750ns or more xlat sqck sqso alock vf0 vf1 vf2 vf3 vf4 vf5 vf6 vf7 signal per0 to 7 fok gfs lock emph alock vf0 to 7 rf jitter amount (used to adjust the focus bias). 8-bit binary data in per0 = lsb, per7 = msb. focus ok high when the frame sync and the insertion protection timing match. high when sampled value of gfs at 460hz is high. low when sampled value of gfs at 460hz is low by 8 times successively. high when the playback disc has emphasis. high when sampled value of gfs at 460hz is high by 8 times successively. low when sampled value of gfs at 460hz is low by 8 times successively. used in cav-w mode. the result obtained by measuring the rotational velocity of the disc. (see the timing chart 2-5.) vf0 = lsb, vf7 = msb. explanation c1f2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 no c1 errors ; c1 pointer reset one c1 error corrected ; c1 pointer reset no c1 errors ; c1 pointer set one c1 error corrected ; c1 pointer set two c1 errors corrected ; c1 pointer set c1 correction impossible ; c1 pointer set c1f1 c1f0 description c2f2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 no c2 errors ; c2 pointer reset one c2 error corrected ; c2 pointer reset two c2 errors corrected ; c2 pointer reset three c2 errors corrected; c2 pointer reset four c2 errors corrected ; c2 pointer reset c2 correction impossible ; c1 pointer copy c2 correction impossible ; c2 pointer set c2f1 c2f0 description ?63 CXD2586R/-1 timing chart 2-5 measurement interval (approximately 3.8 s) reference window (132.2khz) measurement pulse (v16m/2) measurement counter vf0 to 7 load m the relative velocity of the disc can be obtained with the following equation. r = (r: relative velocity, m: measurement results) vf0 to 7 is the result obtained by counting vcki/2 pulses while the reference signal (132.2khz) generated from mclk (384fs) is high. this count is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when dspb is low). m + 1 32 ?64 CXD2586R/-1 ?. description of modes this lsi has three basic operating modes using a combination of spindle control and the pll. the operations for each mode are described below. ?-1. clv-n mode this mode is compatible with the cxd2500 series, and operation is the same (however, variable pitch cannot be used). the pll capture range is 150khz. ?-2. clv-w mode this is the wide capture range mode. this mode allows pll to follow the rotational velocity of the disc. this rotational following control has two types: using the built-in vco2 or providing an external vco. the spindle is the same clv servo as for the cxd2500 series. operation using the built-in vco2 is described below. (when using an external vco, input the signal from the vpco pin to the low-pass filter, use the output from the low- pass filter as the control voltage for the external vco, and input the oscillation from the vco to the vcki pin.) while starting to rotate a disc and/or speeding up to the lock range from the condition that a disc stops, cav-w mode should be used. concretely saying, firstly send $e665x to set cav-w mode and kick a disc, secondly send $e60cx to set clv-w mode if alock is high, which can be read serially from sqso pin. clv-w mode can be used while alock is high. the microcomputer monitors the serial data output, and must return to adjust speed operation (cav-w mode) when alock becomes low. the control flow according to the microcomputer software in clv-w mode is shown in fig. 3-2. in clv-w mode (normal), low power consumption is achieved by setting lpwr to high. control was formerly performed by applying acceleration and deceleration pulses to the spindle motor. however, when lpwr is set to high, deceleration pulses are not output, thereby achieving low power consumption mode. clv-w mode supports control only by the ternary output of the mdp pin. therefore, when using clv-w mode, set dclv pwm md to low. note) the capture range for this mode is theoretically up to the signal processing limit. ?-3. cav-w mode this is the cav mode. in this mode, it is possible to control spindle to variable rotational velocity, the external crystal is fixed though. the rotational velocity is determined by the vp0 to 7 setting values or the external pwm. when controlling the spindle with vp0 to 7, setting the cav-w mode with $e665x command and controlling vp0 to 7 with the $dx commands allows the rotational velocity to be varied from low speed to sextuple-speed. (see $dx commands.) also, when controlling the spindle with the external pwm, the pwmi pin is binary input which becomes kick during high intervals and brake during low intervals. the microcomputer can know the rotational velocity using v16m. and the reference for the velocity measurement is a signal of 132.2khz obtained by 1/128 of mclk (384fs). the velocity is obtained by counting v16m/2 pulses while the reference is high, and the result is output from the new cpu interface as 8 bits (vp0 to 7). these measurement results are 31 when the disc is rotating at normal speed or 127 when it is rotating at quadruple speed. these values match those of the 256-n for control with vp0 to 7. (see table 2-5 and fig. 2- 6.) in cav-w mode, the spindle is set to the desired rotational velocity and the operation speed for the entire system follows this rotational velocity. therefore, the cycles for the fs system clock, pcm data and all other output signals from this lsi change according to the rotational velocity of the disc. note) the capture range for this mode is theoretically up to the signal processing limit. note) set flfc to 1 for this mode. ?65 CXD2586R/-1 cav-w clvs clv-w clvp rotational velocity target velocity operation mode spindle mode time kick lock alock fig. 3-1. disc stop to regular playback in clv-w mode clv-w mode no yes kick $e8000 mute off $a00xxxx alock = h ? no yes alock = l ? clv-w mode start cav-w $e665x (clva) cav-w $e6c00 (clva) (wfck pll) fig. 3-2. clv-w mode flow chart ?66 CXD2586R/-1 ?. description of other functions ?-1. channel clock regeneration by the digital pll circuit the channel clock is needed to demodulate the efm signal regenerated by the optical system. assuming t as the channel clock cycle, the efm signal is modulated in an integer multiple of t from 3t to 11t. in order to read the information in the efm signal, this integer value must be read correctly. as a result, t, that is the channel clock, is necessary. in an actual player, pll is necessary to regenerate the channel clock because the fluctuation in the spindle rotation alters the width of the efm signal pulses. practically, pll is necessary to regenerate the channel clock, because the efm pulse width is altered by spindle rotation fluctuation. the block diagram of this pll is shown in fig. 4-1. the CXD2586R/-1 has a built-in three-stage pll. the first-stage pll is for the wide-band pll. when the built-in vco2 is used, lpf is required externally. when the built-in vco2 is not used, lpf and vco are required externally. the output of this first-stage pll is used as a reference for all clocks within the lsi. the second-stage pll generates a high-frequency clock needed by the third-stage digital pll. the third-stage pll is a digital pll that regenerates the actual channel clock. the digital pll in clv-n mode has a secondary loop, which is the primary loop (phases) and the secondary loop (frequency). when flfc = 1, the secondary loop can be turned off. high-frequency components such as 3t and 4t may contain deviations. in such a case, turning the secondary loop off yields better playability. however, in this case the capture range becomes 50khz. the new digital pll in clv-w mode follows the rotational velocity of the disc, in addition to the above- mentioned secondary loop. ?67 CXD2586R/-1 block diagram 4-1 xtsl 1/2 1/32 1/n 1/2 microcomputer control n = 1 to 256 (vp7 to 0) 1/k (ksl1, 0) clv-w cav-w spindle rotation information clv-n clv-w cav-w /clv-n phase comparator selector lpf 2/1 mux vpon 1/m 1/n vcosel2 vco2 phase comparator vco1 vcosel1 1/k (ksl3, 2) digital pll rfpll vpco1 to 2 vctl v16m vcki pco fili filo cltv cxd2586 mclk clock input ?68 CXD2586R/-1 ?-2. frame sync protection in normal speed playback, a frame sync is recorded approximately every 136 s (7.35khz). this signal is used as a reference to recognize the data within a frame. conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. as a result, recognizing the frame sync properly is extremely important for improving playability. in the CXD2586R/-1, window protection and forward protection/backward protection have been adopted for frame sync protection. these functions achieve very powerful frame sync protection. there are two window widths: one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (wsel = 0/1). in addition, the forward protection counter is fixed to 13, and the backward protection counter to 3. concretely, when the frame sync has been played back normally and then cannot be detected due to scratches, a maximum of 13 frames are inserted. if frame sync cannot be detected for 13 frames or more, the window is released and try to resyncronize the frame sync. in addition, immediately after the window is released and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window is released immediately. ?-3. error correction in the cd format, one 8-bit data contains two error correction codes, c1 and c2. for c1 correction, the code is created with 28-byte information and 4-byte c1 parity. for c2 correction, the code is created with 24-byte information and 4-byte parity. both c1 and c2 are reed solomon codes with a minimum distance of 5. the CXD2586R/-1 uses refined super strategy to achieve double correction for c1 and quadruple correction for c2. in addition, to prevent c2 miscorrection, a c1 pointer is attached to data after c1 correction according to the c1 error status, the playback status of the efm signal, and the operating status of the player. the correction status can be monitored externally. see the table 4-2. when the c2 pointer is high, the data in question was uncorrectable. either the pre-value was held or an average value interpolation was made for the data. mnt3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 no c1 errors ; c1 pointer reset one c1 error corrected ; c1 pointer reset no c1 errors ; c1 pointer set one c1 error corrected ; c1 pointer set two c1 errors corrected ; c1 pointer set c1 correction impossible ; c1 pointer set no c2 errors ; c2 pointer reset one c2 error corrected ; c2 pointer reset two c2 errors corrected ; c2 pointer reset three c2 errors corrected ; c2 pointer reset four c2 errors corrected ; c2 pointer reset c2 correction impossible ; c1 pointer copy c2 correction impossible ; c2 pointer set mnt2 mnt1 mnt0 description table 4-2. ?69 CXD2586R/-1 timing chart 4-3 normal-speed pb 400 to 500ns rfck mnt3 mnt1 mnt0 t = dependent on error condition c1 correction c2 correction strobe strobe mnt2 ?-4. da interface the CXD2586R/-1 has two modes as da interfaces. a) 48-bit slot interface this interface includes 48 cycles of the bit clock within one lrck cycle, and is msb first. when lrck is high, the data is for the left channel. b) 64-bit slot interface this interface includes 64 cycles of the bit clock within one lrck cycle, and is lsb first. when lrck is low, the data is for the left channel. ?70 CXD2586R/-1 timing chart 4-4 lrck (44.1k) da15 (2.12m) wdck da16 lrck (88.2k) da15 (4.23m) wdck da16 48bit slot normal-speed playback pssl = l 1 24 r0 lch msb (15) l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 rmsb lch msb (15) 24 rch msb 23456789101112 48bit slot double-speed playback 12 l0 r0 ?71 CXD2586R/-1 timing chart 4-5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 r15 l ch lsb (0) r ch lsb (0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 20 30 32 31 da12 (44.1k) da13 (2.82m) da14 64 bit slot normal speed pb pssl = l 1 l ch lsb 1 2 3 4 5 10 15 25 da12 (88.2k) da13 (5.64m) da14 64 bit slot double- speed pb 20 30 31 32 r ch lsb (0) 2 3 5 6 7 8 9 10 11 12 13 14 15 4 l15 ?72 CXD2586R/-1 ?-5. digital out there are three digital output formats: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. the cdx2586r/-1 supports type 2 form 1. in addition, regarding the clock accuracy of the channel status, level ii is set for crystal clock use and level iii for cav-w mode. in addition, sub q data which are matched twice in succession after a crc check are input to the first four bits (bits 0 to 3). dout is output when the crystal is 34mhz and dspb is set to 1 with xtsl high in clv-n or clv-w mode. therefore, set md2 to 0 and turn dout off. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 0 id0 id1 copy emph 0 0 0 0 1 0 0 0 0 0 0 0 from sub q 0 16 32 48 176 sub q control bits that matched twice with crcok digital out c bit 12 34 56 78 9101112131415 vpon: 1 crystal: 0 bit0 to 3 bit29 table 4-6. ?73 CXD2586R/-1 ?-6. servo auto sequence this function performs a series of controls, including auto focus and track jumps. when the auto sequence command is received from the cpu, auto focus, 1 track jump, 2n track jumps, fine search, and m track move are executed automatically. servo is used in an exclusive manner during the auto sequence execution (when xbusy = low), so that commands from the cpu are not transferred to the servo, but can be sent to the CXD2586R/-1. in addition, when using the auto sequence, turn the a.seq of register 9 on. when clok goes from low to high while xbusy is low, xbusy does not become high for a maximum of 100 s after that point. this is to prevent the transfer of erroneous data to the servo when xbusy changes from low to high by the monostable multivibrator, which is reset by clok being low (when xbusy is low). in addition, a max timer is built in this lsi as a countermeasure against abnormal operation due to external disturbances, etc. when the auto sequence command is sent from the cpu, this command assumes a $4xy format, in which x specifies the command and y sets the max timer value and timer range. if the executed auto sequence command does not terminate within the set timer value, the auto sequence is interrupted (like $40). see ?, $4x commands concerning the timer value and range. also, the max timer is invalidated by inputting $4x0. although this command is explained in the format of $4x in the following command descriptions, the timer value and timer range are actually sent together from the cpu. (a) auto focus ($47) focus search-up is performed, fok and fzc are checked, and the focus servo is turned on. if $47 is received from the cpu, the focus servo is turned on according to fig. 4-8. the auto focus starts with focus search-up, and note that the pickup should be lowered beforehand (focus search down). in addition, blind e of register 5 is used to eliminate fzc chattering. concretely, the focus servo is turned on at the falling edge of fzc after fzc has been continuously high for a longer time than e. (b) track jump 1, 10, and 2n-track jumps are performed respectively. always use this when focus, tracking and sled servo are on. note that tracking gain-up and braking-on ($17) should be sent beforehand because they are not involved in this sequence. 1-track jump when $48 ($49 for rev) is received from the cpu, a fwd (rev) 1-track jump is performed in accordance with fig. 4-9. set blind a and brake b with register 5. 10-track jump when $4a ($4b for rev) is received from the cpu, a fwd (rev) 10-track jump is performed in accordance with fig. 4-10. the principal difference from the 1-track jump is to kick the sled. in addition, after kicking the actuator, when 5 tracks have been counted through cout, the brake is applied to the actuator. then, when the actuator speed is found to have slowed up enough (determined by the cout cycle becoming longer than the overflow c set in register 5), the tracking and sled servos are turned on. ?74 CXD2586R/-1 2n-track jump when $4c ($4d for rev) is received from the cpu, a fwd (rev) 2n-track jump is performed in accordance with fig. 4-11. the track jump count "n" is set in register 7. although n can be set to 2 16 tracks, note that the setting is actually limited by the actuator. cout is used for counting the number of jumps when n is less than 16, and mirr is used when n is 16 or more. although the 2n-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "d", set in register 6. fine search when $44 ($45 for rev) is received from the cpu, a fwd (rev) fine search (n-track jump) is performed in accordance with fig. 4-12. the differences from a 2n-track jump are a higher precision jump achieved by controlling the traverse speed and a longer distance jump achieved by controlling the sled. the track jump count is set in register 7. n can be set to 2 16 tracks. after kicking the actuator and sled, the traverse speed is controlled based on the overflow g. set kick d and f in register 6 and overflow g in register 5. also, sled speed control during traverse can be turned off by causing comp to fall. set the number of tracks during which comp falls in register b. after n tracks have been counted through cout, the brake is applied to the actuator and sled. (this is performed by turning on the tracking servo for the actuator, and by kicking the sled in the opposite direction during the time for kick d set in register 6.) then, the tracking and sled servos are turned on. set overflow g to the speed required to slow up just before the track jump terminates. (the speed should be such that it will come on-track when the tracking servo turns on at the termination of the track jump.) for example, set the target track count n- a for the traverse monitor counter which is set in register b, and comp will be monitored. when the falling edge of this comp is detected, overflow g can be reset. m track move when $4e ($4f for rev) is received from the cpu, a fwd (rev) m track move is performed in accordance with fig. 4-13. m can be set to 2 16 tracks. cout is used for counting the number of moves when m is less than 16, and mirr is used when m is 16 or more. the m track move is executed only by moving the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. in addition, the track and sled servo are turned off after m tracks have been counted through cout or mirr unlike for the other jumps. transfer $25 after the actuator is stabled. ?75 CXD2586R/-1 auto focus focus search up fok = h no yes fzc = h no yes fzc = l no yes end focus servo on check whether fzc is continuously high for the period of time e set with register 5. fig. 4-8 (a). auto focus flow chart xlat $47 latch $03 blind e $08 fok sein (fzc) busy command for ssp fig. 4-8 (b). auto focus timing chart ?76 CXD2586R/-1 1 track no yes end track kick sled servo wait (blind a) cout = track rev kick wait (brake b) track sled servo on fwd kick for rev jump rev kick for rev jump fig. 4-9 (a). 1-track jump flow chart xlat cout busy $48 (rev = $49) latch $28 ($2c) blind a brake b $2c ($28) $25 command for ssp fig. 4-9 (b). 1-track jump timing chart ?77 CXD2586R/-1 10 track no yes end track, sled fwd kick wait (blind a) cout = 5 ? track, rev kick track, sled servo on check whether the cnin cycle is longer than overflow c. (counts cnin 5) no yes c = over-flow ? fig. 4-10 (a). 10-track jump flow chart cout $4a (rev = $4b) latch blind a $2a ($2f) cout 5 count $2e ($2b) over-flow c $25 xlat busy command for ssp fig. 4-10 (b). 10-track jump timing chart ?78 CXD2586R/-1 2n track no yes end track, sled fwd kick wait (blind a) cout (mirr) = n track rev kick track servo on no yes c = over-flow wait (kick d) sled servo on counts cout for the first 16 times and mirr for more times fig. 4-11 (a). 2n-track jump flow chart xlat blind a $2a ($2f) cout (mirr) n count $2e ($2b) over-flow c kick d $26 ($27) $25 $4c (rev = $4d) latch cout (mirr) busy command for ssp fig. 4-11 (b). 2n track jump timing chart ?79 CXD2586R/-1 track servo on sled fwd kick fine search wait (kick d) track sled fwd kick wait (kick f) traverse speed ctrl (over-flow g) cout = n ? track servo on sled rev kick wait (kick d) track sled servo on end yes no fig. 4-12 (a). fine search flow chart traverse speed control (overflow g) & cout n count kick f kick d $26 ($27) $2a ($2f) $27 ($26) $25 $44 (rev = $45) latch xlat cout kick d busy fig. 4-12 (b). fine search timing chart ?80 CXD2586R/-1 m track move no yes end track servo off sled fwd kick wait (blind a) cout (mirr) = m track, sled servo on counts cnin till m < 16. counts mirr till m 3 16. fig. 4-13 (a). m-track move flow chart xlat blind a $22 ($23) cout (mirr) m count $20 $4e (rev = $4f) latch cout (mirr) busy command for servo fig. 4-13 (b). m-track move timing chart ?81 CXD2586R/-1 ?-7. digital clv fig. 4-14 shows the block diagram. digital clv outputs mds error and mdp error with pwm, sampling frequency is 130hz at most during normal-speed playback in clvs, clvp and other modes. in addition, the digital spindle servo gain is variable. mdp digital clv clvs u/d mds error mdp error clv p/s measure measure 2/1 mux over sampling filter-1 gain mds 1/2 mux clv p/s over sampling filter-2 noise shape modulation kick, brake, stop mds mode select + gain dclv gain mdp dclvmd, lpwr pwmi fig. 4-14. block diagram clvs u/d: up/down signal from clvs servo mds error: frequency error for clvp servo mdp error: phase error for clvp servo pwmi: spindle drive signal from the microcomputer ?82 CXD2586R/-1 ?-8. playback speed in the CXD2586R/-1, the following playback modes can be selected through different combinations of mclk, xtsl pin, double-speed command (dspb), vco1 selection command (vcosel1), vco1 frequency dividing command (ksl3, ksl2) and command transfer rate selector (ashs) in clv-n or clv-w mode. for the CXD2586R/-1 mode 1 2 3 4 5 6 7 8 9 10 11 mclk 1152fs 1152fs 1152fs 1152fs 768fs 768fs 768fs 768fs 384fs 384fs 384fs xtsl 1 1 0 0 1 1 0 0 0 0 1 dspb 0 1 0 1 0 1 0 1 0 1 1 vcosel1 * 1 0/1 1 1 1 0/1 0/1 1 1 0/1 0/1 0/1 ashs 1 1 * 2 * 2 0 0 1 1 0 0 0 playback speed 1.5 3 3 6 1 2 2 4 1 2 1 error correction c1: double; c2: quadruple c1: double; c2: double c1: double; c2: quadruple c1: double; c2: double c1: double; c2: quadruple c1: double; c2: double c1: double; c2: quadruple c1: double; c2: double c1: double; c2: quadruple c1: double; c2: double c1: double; c2: double * 1 actually, use the optimal value by combining ksl3 with ksl2. * 2 the built-in auto sequencer can not be used. the playback speed can be varied by setting vp0 to 7 in cav-w mode. see "?. description of modes" for details. ?83 CXD2586R/-1 ?-9. dac block playback conditions the dac block playback speed is controlled by sending the dads command to the dsp block. mode 1 2 768fs 384fs 0 1 x'tal dads ?-10. dac block input timing the timing charts for input to the dac are shown below. in the CXD2586R/-1, audio data is not sent from the cd signal processor block to the dac block inside the lsi. the reason why is to allow data to be passed through an audio dsp, etc., on its way to the dac block. to input data to the dac block without passing it through an audio dsp, etc., the data connection must be made externally. in this case, lrck, bck, and pcmd can be connected directly to lrcki, bcki, and pcmdi. (see the application circuit.) normal-speed playback l15 invalid l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 l0 lrcki (44.1k) bcki (2.12m) pcmdi ?84 CXD2586R/-1 lpf block the CXD2586R/-1 contains an initial-stage secondary active lpf with numerous resistors and capacitors and an operational amplifier with reference voltage. the resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly. the reference voltage (vc) is (av dd ?av ss )/2. the lpf block application circuit is shown below. in this circuit, the cut-off frequency is fc 40khz. the capacitance of the external capacitors when fc = 30khz and 50khz are noted below as a reference. when fc 30khz: c1 = 200pf, c2 = 910pf when fc 50khz: c1 = 120pf, c2 = 560pf lpf block application circuit 58 57 56 12k 12k 12k c1 150p c2 680p aout1 ain1 lout1 vc analog out lpf external circuit ?85 CXD2586R/-1 ?-11. CXD2586R/-1 clock system the dac, digital signal processor and digital servo blocks can be switched to each playback mode according to how the crystal and clock circuit are connected. each circuit is as shown in the diagram below; during normal use, mcko and mclk are directly connected to each other, and fsto and fsti are directly connected to each other. 384fs or 768fs xtli xtlo osc dads (command register) clock supplied to dac 384fs to dac block to digital signal processor block xtsl mcko mclk external connection fsto fsti external connection 128fs to digital servo block xt2d xt4d (command register) 1/2 1/2 2/3 1/2 1/4 ?86 CXD2586R/-1 [5] description of servo signal processing-system functions and commands ?-1. general description of the servo signal processing system (voltages are the values for a 5v power supply.) focus servo sampling rate: 88.2khz input range: 2.5v center 1.0v output format: 7-bit pwm others: offset cancel focus bias adjustment focus search gain-down function defect countermeasure automatic gain control tracking servo sampling rate: 88.2khz input range: 2.5v center 1.0v output format: 7-bit pwm others: offset cancel e:f balance adjustment track jump gain-up function defect countermeasure drive cancel automatic gain control vibration countermeasure sled servo sampling rate: 345hz input range: 2.5v center 1.0v output format: 7-bit pwm others: sled move fok, mirr, dfct signals generation rf signal sampling rate: 1.4mhz input range: 2.15v to 5.0v others: rf zero level automatic measurement the signal input from the rfdc pin is multiplied by a factor of 0.7 and loaded into the a/d converter. ?87 CXD2586R/-1 ?-2. digital servo block master clock (mck) the fsti pin is the reference clock input pin. the internal master clock (mck) is generated by dividing the frequency of the signal input to fsti. the frequency division ratio is 1/2 or 1/4. table 3-1 below shows the hypothetical case where the crystal clock generated from the digital signal processor block is 2/3 frequency-divided and input to the fsti pin by externally connecting the fsti pin and the fsto pin. the xt4d and xt2d command settings can be made with d13 and d12 of $3f. (default = 0) the digital servo block is designed with an mck frequency of 5.6448mhz. mode 1 2 3 4 384fs 384fs 768fs 768fs 256fs 256fs 512fs 512fs 256fs 256fs 512fs 512fs * 0 * 1 0 0 1 0 1 0 0 0 1/2 1/2 1/4 1/4 128fs 128fs 128fs 128fs mclk fsto fsti xtsl xt4d xt2d frequency division ratio mck frequency fs = 44.1khz, * : don? care table 5-1. ?-3. avrg (average) measurement and compensation the CXD2586R/-1 has a circuit that measures avrg of rfdc, vc, fe, and te and a circuit that compensates them to control servo effectively. avrg measurement and compensation is necessary to initialize the CXD2586R/-1, and is able to cancel the offset by performing each avrg measurement before playback operation and using these results for compensation. the level applied to the vc, fe rfdc and te pins can be measured by setting d15 (vclm), d13 (flm), d11 (rflm) and d4 (tclm) of $38 respectively to 1. avrg measurement consists of digitally measuring the level applied to each analog input pin by taking the average of 256 samples, and then loading these values into the avrg register. avrg measurement requires approximately 2.9ms to 5.8ms after the command is received. during avrg measurement, if the upper 8 bits of the serial command are 38 (hex), the completion of avrg measurement operation can be confirmed through the sens pin. (see the timing chart 5-2.) xlat sens (= xavebsy) max. 1 s completion of avrg measurement 2.9 to 5.8ms timing chart 5-2. ?88 CXD2586R/-1 ?89 CXD2586R/-1 ?-4. e:f balance adjustment function when the disc is rotated with the laser on, and with the fcs (focus) servo on via fcs search (focus search), the traverse waveform appears in the te signal due to disc eccentricity. in this condition, the low-frequency component can be extracted from the te signal using the built-in trk hold filter by setting d5 (tblm) of $38 to 1. the extracted low-frequency component is loaded into the trvsc register as a digital value, and the trvsc register value is established when tblm returns to 0. next, setting d2 (tlc2) of $38 to 1 applies only the amount of compensation (subtraction) equal to the trvsc register value to the values obtained from the te and se input pins, enabling the e:f balance offset to be adjusted. (see fig. 5-3.) ?-5. fcs bias (focus bias) adjustment function the fbias register value can be added to the fcs servo filter input by setting d14 (fbon) of $3a to 1. (see fig. 3-3.) when the fbias register value is set to d11 = 0 and d10 = 1 by $34f, data can be written using the 9-bit value of d9 to d1 (d9: msb). in addition, the rf jitter can be monitored by setting the scot command of $8 to 1. (see the dsp block timing chart.) the fbias register can be used as a counter by setting d13 (fbss) of $3a to 1. it works as an up/down counter. the fbias register works as an up counter when d12 (fbup) of $3a = 1, and as a down counter when d12 (fbup) of $3a = 0. the number of up and down steps can be changed by setting d11 and 10 (fbv1 and fbv0) of $3a. when using the fbias register as a counter, the counter stops when the value set beforehand in fbl9 to 1 of $34 matches the fcsbias value. also, if the upper 8 bits of the serial command are $3a at this time, the counter stop can be monitored through sens. abc fbias setting value (fb9 to 1) limit value (fbl9 to 1) sens pin a: register mode b: counter mode c: counter mode (when stopped) here, the fbias setting values fb9 to 1 and the fbias limit values fbl9 to 1 are assumed to be set in status a. for example, if command registers fbup = 0, fbv1 = 0, fbv0 = 0 and fbss = 1 are set from this status, down count starts from status a and approaches the set limit value. when the limit value is reached and the fbias value matches fbl9 to 1, the counter stops and the sens pin goes to high. note that the up/down counter changes with each sampling cycle of the focus servo filter. the number of steps by which the count value changes can be selected from 1, 2, 4 or 8 steps by fbv1 and fbv0. when converted to fe input, 1 step corresponds to approximately 3.9 [mv]. ?90 CXD2586R/-1 te avrg register tlc1 trvsc register tlc2 to trk/sld in register vc avrg register tlc0 vclc te, se from a/d fe avrg register flc1 fbias register fbon ? to fcs in register flc0 to fzc register fe from a/d rflc to rf in register rfdc from a/d rf avrg register fig. 5-3. ?91 CXD2586R/-1 ?-6. agcntl (automatic gain control) function the agcntl function automatically adjusts the filter internal gain in order to obtain the appropriate gain with the servo loop. agcntl not only copes with the sensitivity variation of the actuator and photo diode, etc., but also obtains the optimal gain for each disc. the agcntl command is sent when each servo is turned on. during agcntl operation, if the upper 8 bits of the serial command are 38 (hex), the completion of agcntl operation can be confirmed through the sens pin. (see the timing chart 5-4 and the description of sens signals.) setting d9 and d8 of $38 to 1 set fcs (focus) and trk (tracking) respectively to agcntl operation. note) during agcntl operation, each servo filter gain must be normal, and the anti-shock circuit (described hereafter) must be disabled. xlat sens (= agok) max. 11.4 s agcntl termination timing chart 5-4. coefficient k13 changes for agf (focus agcntl) and coefficients k23 and k07 changes for agt (tracking agcntl) due to agcntl. these coefficients change from 01 to 7f (hex), and they must also be set within this range when written externally. after agcntl operation has terminated, these coefficient values can be confirmed by reading them out from the sens pin with the serial readout function (described hereafter). agcntl related setting the following settings can be changed with $35, $36 and $37. fg6 to fg0; agf convergence gain setting, effective setting range: 00 to 57 (hex) tg6 to tg0; agt convergence gain setting, effective setting range: 00 to 57 (hex) ags; self-stop on/off agj; convergence completion judgment time aggf; internally generated sine wave amplitude (agf) aggt; internally generated sine wave amplitude (agt) agv1; agcntl sensitivity 1 (during high sensitivity adjustment) agv2; agcntl sensitivity 2 (during low sensitivity adjustment) aghs; high sensitivity adjustment on/off aght; high sensitivity adjustment time note) converging servo loop gain values can be changed with the fg6 to 0 and tg6 to 0 setting values. in addition, these setting values must be within the effective setting range. the default settings aim for 0db at 1khz. however, since convergence values vary according to the characteristics of each constituent element of the servo loop, fg and tg values should be set as necessary. ?92 CXD2586R/-1 agcntl and default operation have two stages. in the first stage, high sensitivity adjustment is performed for a certain period of time (select 256/128ms with aght), and the agcntl coefficient approaches the appropriate value roughly. the sensitivity at this time can be selected from two types with agv1. in the second stage, the agcntl coefficient approaches the appropriate value finely with relatively low sensitivity. the sensitivity for the second stage can be selected from two types with agv2. in the second stage of default operation, when the agcntl coefficient reaches the appropriate value and stops changing, the CXD2586R/-1 confirms that the agcntl coefficient has not changed for a certain period of time (select 63/31ms with aghj), and then terminates agcntl operation. (self-stop mode) this self-stop mode can be canceled by setting ags to 0. in addition, the first stage is omitted for agcntl operation when aghs is set to 0. an example of agcntl coefficient transitions during agcntl operation and the relationship between the various settings are shown in fig. 5-5. initial value sens agcntl start agcntl completion convergence value agcntl coefficient value slope agv1 aght agj slope agv2 fig. 5-5. ?93 CXD2586R/-1 ?-7. fcs servo and fcs search (focus search) the fcs servo is controlled by the 8-bit serial command $0x. (see table 5-6.) register name command d23 to d20 d19 to d16 10 ** 11 ** 0 * 0 * 0 * 1 * 0 * 10 0 * 11 focus servo on (focus gain normal) focus servo on (focus gain down) focus servo off, 0v out focus servo off, focus search voltage out focus search voltage down focus search voltage up 00 00 focus control 0 table 5-6. fcs search fcs search is required in the course of turning on the fcs servo. fig. 5-7 shows the signals for sending commands $00 ? $02 ? $03 and performing only fcs search. fig. 5-8 shows the signals for sending $08 (fcs on) after that. fcsdrv rf fok fe fzc fzc comparator level $00 $02 $03 0 0 fcsdrv rf fok fe fzc $00 $02 $03 0 $08 fig. 5-7. fig. 5-8. * : don? care ?94 CXD2586R/-1 ?-8. trk (tracking) and sld (sled) servo control trk and sld servo is controlled by the 8-bit command $2x. (see table 5-9.) when the upper 4 bits of the serial command are 2 (hex), tzc is output from the sens pin. 00 ** 01 ** 10 ** 11 ** ** 00 ** 01 ** 10 ** 11 tracking servo off tracking servo on forward track jump reverse track jump sled servo off sled servo on forward sled move reverse sled move 00 10 tracking mode 2 table 5-9. trk servo the trk jump (track jump) height can be set with the 6 bits d13 to d8 of $36. in addition, when the trk servo is on and d17 of $1 is set to 1, the trk servo filter assumes gain-up status. the trk servo filter also assumes gain-up status when vibration detection is performed with the lock signal low and the anti-shock circuit (described hereafter) enabled. the gain-up filter used when trk has assumed gain-up status has two types of structures which can be selected by setting d16 of $1. (see table 5-17.) sld servo the sld mov (sled move) output, composed of a basic value from the 6 bits d13 to d8 of $37, is determined by multiplying this value by 1, 2, 3, or 4 magnification set using d17 and d16 when d19 = d18 = 0 is set with $3. (see table 5-10.) sld mov must be performed continuously for 50 s or more. in addition, if the lock input signal goes low when the sld servo is on, the sld servo turns off. note) when the lock signal is low, the trk servo is set gain-up status and the sld servo is turned off, by the default. this is disabled by setting d6 (lksw) of $38 to 1. 00 00 00 01 00 10 00 11 sled kick level (basic value ?) sled kick level (basic value ?) sled kick level (basic value ?) sled kick level (basic value ?) 00 11 select 3 table 5-10. * : don? care register name command d23 to d20 d19 to d16 register name command d23 to d20 d19 to d16 ?95 CXD2586R/-1 ?-9. mirr and dfct signal generation the rf signal obtained from the rfdc pin is sampled at approximately 1.4mhz and loaded. the mirr and dfct signals are generated from this rf signal. mirr signal generation the loaded rf signal is applied to peak hold and bottom hold circuits. an envelope is generated from the waveforms generated in these circuits, and the mirr comparator level is generated from the average of these envelope waveforms. the mirr signal is generated by comparing this mirr comparator level with the waveform generated by subtracting the bottom hold value from the peak hold value. (see fig. 5-11.) rf peak hold bottom hold peak hold ?ottom hold mirr mirr comp (mirror comparator level) h l rf peak hold1 peak hold2 peak hold2 ?eak hold1 dfct (defect comparator level) h l sdf fig. 5-11. dfct signal generation the loaded rf signal is input to two peak hold circuits with different time constants, and the dfct signal is generated by comparing the difference between these two peak hold waveforms with the dfct comparator level. (see fig. 5-12.) the dfct comparator level can be selected from four values using d13 and d12 of $3b. fig. 5-12. ?96 CXD2586R/-1 ?-10. dfct countermeasure circuit the dfct countermeasure circuit performs operations to maintain the directionality of the servo so that the servo does not become easily dislocated due to scratches or defects on discs. specifically, these operations are achieved by performing scratch and defect detection with the dfct signal generation circuit, and when dfct goes high, applying the low frequency component of the error signal before dfct went high to the fcs and trk servo filter inputs. (see fig. 5-13.) in addition, these operations are activated by the default. they can be disabled by setting d7 (dfsw) of $38 to 1 or by inputting high level to the dfsw pin. input register hold register hold filter servo filter en error signal dfct fig. 5-13. ?-11. anti-shock circuit when vibrations are produced in the cd player, this circuit forces the trk filter to assume gain-up status so that the servo does not become easily dislocated. this circuit is for systems which require vibration countermeasures. concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is increased. (see fig. 5-14.) the comparator level is fixed to 1/16 of the maximum comparator input amplitude. however, the comparator level is practically variable by the anti-shock filter output coefficient k35. this function can be turned on and off by d19 of $1 when the brake circuit (described hereafter) is off. (see table 5-17.) this circuit can also support an external vibration detection circuit, and can also set the trk servo filter to gain-up status by inputting high level to the atsk pin. when the serial command is $1, vibration detection can be monitored from the sens pin. te anti shock filter trk gain up filter trk gain normal filter trk pwm gen atsk sens comparator fig. 5-14. ?97 CXD2586R/-1 ?-12. brake circuit immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to turn on. the brake circuit prevents these phenomenon. in principle, this circuit cuts unnecessary portions of the tracking drive and works it as the brake by utilizing the 180 offset in the rf envelope and tracking error phase relationship which occurs when the actuator traverses the track in the radial direction from the inner track to the outer track and vice versa. (see figs. 5-15 and 5-16.) concretely, this operation is achieved by masking the tracking drive using the trkcncl signal generated by loading the mirr signal at the edge of the tzc (tracking zero cross) signal. the brake circuit can be turned on and off by d18 of $1. (see fig. 5-17.) trk drv fwd jmp rev jmp servo on rf trace mirr te 0 0 tzc edge trkcncl trk drv sens tzc out inner track outer track trk drv rev jmp fwd jmp servo on rf trace mirr te 0 0 tzc edge trkcncl trk drv sens tzc out outer track inner track fig. 5-15. fig. 5-16. 10 ** 0 *** * 1 ** * 0 ** ** 0 * ** 1 * ** * 1 ** * 0 anti shock on anti shock off brake on brake off tracking gain normal tracking gain up tracking gain up filter select 1 tracking gain up filter select 2 00 01 tracking control 1 fig. 5-17. * : don? care register name command d23 to d20 d19 to d16 ?98 CXD2586R/-1 ?-13. cout signal the cout signal is output to count the number of tracks during traverse, etc. it is basically generated by loading the mirr signal at both edges of the tzc signal. however, the used tzc signal can be selected and there are two types of output methods according to the cout signal application. for 1-track jumps, etc. fast phase cout signal with a fast phase tzc signal. for high-speed traverse reliable cout signal with a delayed phase tzc signal. this is because some time is required to generate the mirr signal, and it is necessary to delay the tzc signal in accordance with the mirr signal delay during high-speed traverse. the cout signal output method is switched with d16 when d19 = d18 = 1 and d17 = 0 are set with $3. (when d16 = 1, for delayed phase and high-speed traverse.) in addition, the tzc signal delay can be selected from two values with d14 of $36. ?-14. serial readout circuit the following measurement and adjustment results can be read out from the sens pin by inputting the readout clock to the sclk pin by $39. (see fig. 5-18, table 5-19 and the description of sens signals.) specified commands $390c vc avrg measurement result $3908 fe avrg measurement result $3904 te avrg measurement result $391f rf avrg measurement result $3953 fcs agcntl coefficient result $3963 trk agcntl coefficient result $391c trvsc adjustment result $391d fbias register value ?? ?? t dls t spw 1/f sclk msb lsb xlat sclk serial read out data (sens) item symbol min. typ. max. unit sclk frequency sclk pulse width delay time f sclk t spw t dls 500 15 1 mhz ns ? table 5-19. during readout, the upper 8 bits of the serial data must be 39 (hex). fig. 5-18. ?99 CXD2586R/-1 ?-15. writing the coefficient ram the coefficient ram can be rewritten by $34. all coefficients have default values in the built-in rom, and transfer from the rom to the ram is completed approximately 40 s after the xrst pin rises. (the coefficient ram cannot be rewritten during this period.) after that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address of the coefficient ram. the coefficient rewrite command is comprised of 24 bits, with d14 to d8 of $34 as the address (d15 = 0) and d7 to d0 as data. ?-16. pwm output fcs, trk and sld outputs are output as pwm waveforms. in particular, fcs and trk permit accurate drive by using a double oversampling noise shaper. timing chart 5-20 and figs. 5-21 and 5-22 show examples of output waveforms and drive circuits. the on signal (fon and ron) is active low. t mck = 180ns timing chart 5-20. 64t mck 64t mck 64t mck at mck 1t mck at mck sfon sfdr sron srdr sld 32t mck 32t mck 32t mck 32t mck 32t mck 32t mck 1t mck 1t mck 1t mck 1t mck ffon/ tfon fcs/trk ffdr/ tfdr fron/ tron frdr/ trdr output value +a output value ? output value 0 1t mck t mck a 2 t mck a 2 t mck a 2 t mck a 2 mck (5.6448mhz) - - - - - - - 1 5.6448mhz ?100 CXD2586R/-1 example of driver circuits fon rdr ron fdr drv drv+ gnd v dd fig. 5-21. pwm bridge drive circuit rdr fdr 22k 22k 22k 22k drv v cc v ee fig. 5-22. operational amplifier drive circuit ?101 CXD2586R/-1 ?-17. dirc input pin the $2 command register can be changed by operating the dirc input pin. using the dirc pin allows serial data transfer to be simplified during trkjmp. fig. 5-23 shows $2 command register changes produced by dirc pin changes. in addition, timing chart 5-24 shows dirc-based operations during trkjmp. high level must be input to the dirc pin when the xrst pin rises from low to high. q3 0 0 1 1 q2 0 1 0 1 servo status off on fwd jmp rev jmp q3 1 1 1 1 q2 1 0 1 0 servo status rev jmp fwd jmp rev jmp fwd jmp q3 0 0 0 0 q2 1 1 1 1 servo status on on on on q1 0 0 1 1 q0 0 1 0 1 servo status off on fwd mov rev mov q1 0 0 1 1 q0 0 1 0 1 servo status off on fwd mov rev mov q1 0 0 1 1 q0 1 1 0 1 servo status on on fwd mov rev mov dirc trk sld q3, q2, q1 and q0 correspond to d19, d18, d17 and d16 of $2. fig. 5-23. $28 latch on off off on on off on off $2c latch xlat dirc fwd jump rev jump trk servo sld servo timing chart 5-24. ?102 CXD2586R/-1 ?-18. servo status changes produced by the lock signal when the lock signal becomes low, the trk servo assumes the gain-up status and the sld servo turns off in order to prevent sld free-running. setting d6 (lksw) of $38 to 1 deactivates this function. in other words, neither the trk servo nor the sld servo change even when the lock signal becomes low. this enables microcomputer control. ?-19. description of commands and data sets the following description contains portions which convert internal voltages into the values when they are output externally and describe them as input conversion or output conversion. input conversion converts these voltages into the voltages entering input pins before a/d conversion. output conversion converts pwm output values into analog voltage values. both types of conversion are calculated at v dd = 5.0v. if this voltage changes, the conversion values also change proportionally. (voltage conversion = v ddx /5; v ddx : used supply voltage) ?103 CXD2586R/-1 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 ka6 ka5 ka4 ka3 ka2 ka1 ka0 kd7 kd6 kd5 kd4 kd3 kd2 kd1 kd0 when d15 = 0 ka6 to ka0: coefficient address kd7 to kd0: coefficient data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 0 1 fb9 fb8 fb7 fb6 fb5 fb4 fb3 fb2 fb1 when d15 = d14 = d13 = d12 = 1. ($34f) d11 = 0, d10 = 1 fbias register write fb9 to fb1: data; fb9 is msb two's complement data. for fe input conversion, fb9 to fb1 = 011111111 corresponds to approximately +1v and fb9 to fb1 = 100000000 to ?v respectively. (when the supply voltage = 5v) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 0 fbl9 fbl8 fbl7 fbl6 fbl5 fbl4 fbl3 fbl2 fbl1 when d15 = d14 = d13 = d12 = d11 = 1 ($34f) d10 = 0 fbias limit register write fbl9 to fbl1: data; data compared with fb9 to 1, fbl9 = msb. when using the fbias register in counter mode, counter operation stops when the value of fb9 to 1 matches fbl9 to 1. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 0 0 tv9 tv8 tv7 tv6 tv5 tv4 tv3 tv2 tv1 tv0 when d15 = d14 = d13 = d12 = 1. ($34f) d11 = 0, d10 = 1 trvsc register write tv9 to tv0: data; tv9 is msb two's complement data. for te input conversion, tv9 to tv0 = 0011111111 corresponds to approximately +1v and tv9 to tv0 = 1100000000 to ?v respectively. (when the supply voltage = 5v) note) when the trvsc register is read out, the data length is 9 bits. at this time, data corresponding to each bit of tv8 to tv0 during external write are read out. when reading out internally measured values and then writing these values externally, set tv9 the same as tv8. $34 ?104 CXD2586R/-1 $35 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ft1 ft0 fs5 fs4 fs3 fs2 fs1 fs0 ftz fg6 fg5 fg4 fg3 fg2 fg1 fg0 ft1, ft0, ftz: focus search-up speed default value: 010 (3.36v/s) focus drive output conversion ft1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 6.73 v/s 3.36 2.24 1.68 8.97 5.38 4.49 3.85 ft0 ftz focus search speed fs5 to fs0: focus search limit voltage default value: 011000 ( 1.875v) focus drive output conversion fg6 to fg0: agf convergence gain setting value default value: 0101101 $36 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 dtzc tj5 tj4 tj3 tj2 tj1 tj0 sfjp tg6 tg5 tg4 tg3 tg2 tg1 tg0 dtzc: dtzc delay (8.5/4.25 s) default value: 0 (4.25 s) tj5 to tj0: track jump voltage default value: 001110 ( 1.09v) tracking drive output conversion sfjp: surf jump mode on/off trk pwm output is made by adding the tracking filter output and tjreg (tj5 to 0), by setting d7 to 1 (on). tg6 to tg0: agt convergence gain setting value default value: 0101110 ?105 CXD2586R/-1 $37 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 fzsh fzsl sm5 sm4 sm3 sm2 sm1 sm0 ags agj aggf aggt agv1 agv2 aghs aght fzsh, fzsl: fzc (focus zero cross) slice level default value:01 ( 250mv); fe input conversion fzsh 0 0 1 1 0 1 0 1 +500mv +250 +125 +62.5 fzsl slice level sm5 to sm0: sled move voltage default value: 010000 ( 1.25v) sled drive output conversion ags: agcntl self-stop on/off default value: 1 (on) agj: agcntl convergence completion judgment time during low sensitivity adjustment (31/63ms) default value: 0 (63ms) aggf: focus agcntl internally generated sine wave amplitude (small/large) default value: 1 (large) aggt: tracking agcntl internally generated sine wave amplitude (small/large) default value: 1 (large) aggf 0 (small) 1 (large) 63mv 125 125mv 250 aggt 0 (small) 1 (large) fe/te input conversion agv1: agcntl convergence sensitivity during high sensitivity adjustment; high/low default value: 1 (high) agv2: agcntl convergence sensitivity during low sensitivity adjustment; high/low default value: 0 (low) aghs: agcntl high sensitivity adjustment on/off default value: 1 (on) aght: agcntl high sensitivity adjustment time (128/256ms) default value: 0 (256ms) ?106 CXD2586R/-1 $38 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 vclm vclc flm flc0 rflm rflc agf agt dfsw lksw tblm tclm flc1 tlc2 tlc1 tlc0 vclm: vc level measurement (on/off) vclc: vc level compensation for fcs in register (on/off) flm: focus zero level measurement (on/off) flc0: focus zero level compensation for fzc register (on/off) rflm: rf zero level measurement (on/off) rflc: rf zero level compensation (on/off) agf: focus automatic gain adjustment (on/off) agt: tracking automatic gain adjustment (on/off) dfsw: defect disable switch (on/off) setting this switch to 1 (on) disables the defect countermeasure circuit. lksw: lock switch (on/off) setting this switch to 1 disables the sled free-running prevention circuit. tblm: traverse center measurement (on/off) tclm: tracking zero level measurement (on/off) flc1: focus zero level compensation for fcs in register (on/off) tlc2: traverse center compensation (on/off) tlc1: tracking zero level compensation (on/off) tlc0: vc level compensation for trk/sld in register (on/off) note) commands marked with are accepted every 2.9ms. all commands are on when set to 1. ?107 CXD2586R/-1 sd6 1 0 0 1 0 address = data ram data for (sd4 to sd0) address = coefficient ram data for (sd5 to sd0) sd4 1 0 sd3 to sd0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 1 ** 1 0 ** 0 1 ** 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 rf avrg register rfdc input signal fbias register trvsc register rfdc envelope (bottom) rfdc envelope (peak) vc avrg register fe avrg register te avrg register fe input signal te input signal se input signal vc input signal 8 bits 8 bits 9 bits 9 bits 8 bits 8 bits 9 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits 8 bits 16 bits sd5 readout data readout data length note) coefficients k40 to k4f cannot be read out. * : don? care see the description for sro1 and sro0 of $3f concerning readout methods for the above data. d15 d14 d13 d12 d11 d10 d9 d8 dac sd6 sd5 sd4 sd3 sd2 sd1 sd0 dac: serial data readout dac mode (on/off) sd6 to sd0: serial readout data select $39 ?108 CXD2586R/-1 $3a d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 fbon fbss fbup fbv1 fbv0 0 tjd0 fps1 fps0 tps1 tps0 ceit sjhd inbk mti0 fbon: fbias (focus bias) register addition (on/off) the fbias register value is added to the signal loaded into the fcs in register by setting d14 to 1 (on). fbss: fbias (focus bias) register/counter switching the fcs bias register can be used as a counter by setting d13 to 1 (on). fbup: fbias (focus bias) counter up/down operation switching this performs counter up/down control when fbss = 1. the fbias register functions as a down counter when d12 is set to 0, and as an up counter when set to 1. fbv1, fbv0: fbias (focus bias) counter voltage switching fcs bias count up steps is decided by these bits. tjd0: this sets the tracking servo filter data ram to 0 when switched from track jump to servo on only when sfjp = 1 (during surf jump operation). fps1, fps0: gain setting when transferring data from the focus filter to the pwm block. tps1, tps0: gain setting when transferring data from the tracking filter to the pwm block. this is effective for increasing the overall gain in order to widen the servo band. operation when fps1, fps0 (tps1, tps0) = 00 is the same as usual (7-bit shift). however, 6db, 12db and 18db can be selected independently for focus (tracking) by setting the relative gain to 0db when fps1, fps0 (tps1, tps0) = 00. ceit: the ce pin input takes over the te pin input by setting d3 to 1 (on). this means that the registers and filters for te input are used for ce input. sjhd: this holds the tracking filter output at the value when surf jump starts during surf jump. inbk: when d1 is 0 (off), the brake circuit masks the tracking filter output signal with the trkcncl which is generated by taking the mirr signal at the tzc edge. when d1 is set to 1 (on), the tracking filter input is masked instead of the output. mti0: the tracking filter input is masked when the mirr signal is high by setting d0 to 1 (on). the counter changes once for each sampling cycle of the focus servo filter. when mck is 128fs, the sampling frequency is 88.2khz. when converted to fe input, 1 step is approximately 3.9 [mv]. fbv1 0 0 1 1 0 1 0 1 1 2 4 8 fbv0 number of steps fps1 0 0 1 1 fps0 0 1 0 1 0db +6db +12db +18db relative gain tps1 0 0 1 1 tps0 0 1 0 1 0db +6db +12db +18db relative gain ?109 CXD2586R/-1 $3b sfox, sfo2, sfo1: fok slice level default value: 011 (313mv) rfdc input conversion sfox 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 179mv 223 268 313 357 446 536 625 sfo2 0 1 0 1 0 1 0 1 sfo1 slice level d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sfo2 sfo1 sdf2 sdf1 max2 max1 sfox btf d2v2 d2v1 d1v2 d1v1 rint 0 0 0 ?110 CXD2586R/-1 sdf2,sdf1: dfct slice level default value: 10 (179mv) rfdc input conversion sdf2 0 0 1 1 0 1 0 1 89mv 134 179 224 sdf1 slice level max2, max1: dfct maximum time default value: 00 (no timer limit) max2 0 0 1 1 0 1 0 1 no timer limit 2.00ms 2.36 2.72 max1 dfct maximum time btf: bottom hold double-speed count-up mode for mirr signal generation on/off (default: off) on when set to 1. d2v2, d2v1: peak hold 2 for dfct signal generation count-down speed setting default value: 01 (0.492v/ms, 44.1khz) [v/ms] unit items indicate rfdc input conversion; [khz] unit items indicate the operating frequency of the internal counter. d1v2, d1v1: peak hold 1 for dfct signal generation count down speed setting default value: 01 (3.938v/ms, 352.8khz) [v/ms] unit items indicate rfdc input conversion; [khz] unit items indicate the operating frequency of the internal counter. rint: this initializes the initial-stage registers of the circuits which generate mirr, dfct and fok. d2v2 0 0 1 1 0 1 0 1 22.05 44.1 88.2 176.4 0.246 0.492 0.984 1.969 d2v1 count-down speed [v/ms] [khz] 176.4 352.8 705.6 1411.2 1.969 3.938 7.875 15.75 d1v2 0 0 1 1 0 1 0 1 d1v1 count-down speed [v/ms] [khz] ?111 CXD2586R/-1 $3e f1nm, f1dm: quasi double accuracy setting for fcs servo filter first-stage on when set to 1; default = 0. f1nm: gain normal f1dm: gain down t1nm, t1um: quasi double accuracy setting for trk servo filter first-stage on when set to 1; default = 0. t1nm: gain normal t1um: gain up f3nm, f3dm: quasi double accuracy setting for fcs servo filter third-stage on when set to 1; default = 0. generally, the advance amount of the phase becomes large by partially setting the fcs servo third-stage filter which is used as the phase compensation filter to double accuracy. f3nm: gain normal f3dm: gain down t3nm, t3um: quasi double accuracy setting for trk servo filter third-stage on when set to 1; default = 0. generally, the advance amount of the phase becomes large by partially setting the trk servo third-stage filter which is used as the phase compensation filter to double accuracy. t3nm: gain normal t3um: gain up note) filter first- and third-stage quasi double accuracy settings can be set individually. see filter composition at the end of this specification concerning quasi double-accuracy. dfis: fcs hold filter input extraction node selection 0: m05 (data ram address 05); default 1: m04 (data ram address 04) tlcd: this command masks the tlc2 command set by d2 of $38 only when fok is low. on when set to 1; default = 0 rflp: this command passes the signal obtained from the rfdc pin through the lpf (low pass filter) before the built-in a/d converter. 0: lpf off; default 1: lpf on miri: mirr input switching. the mirr signal can be input from an external source. when d1 is 0, the mirr signal is used internally as usual. when d1 = 1, the mirr signal can be input from an external source through the mirr pin. xt1d: the clock input from fsti can be used as the master clock for the servo block regardless of the xtsl pin, xt2d and xt4d by setting d0 to 1. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 f1nm f1dm f3nm f3dm t1nm t1um t3nm t3um dfis tlcd rflp 0 0 0 miri xt1d ?112 CXD2586R/-1 $3f d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 agg4 xt4d xt2d 0 drr2 drr1 drr0 0 asfg 0 lpas sro1 sro0 aghf cot2 xt4d, xt2d: mck (digital servo master clock) frequency division setting this command forcibly sets the frequency division ratio to 1/2 or 1/4 when mck is generated from the signal input to the fsti pin. agg4: this varies the amplitude of the internally generated sine wave using the aggf and aggt commands during agc. when agg4 = 0, the default is used. when agg4 = 1, the setting is as shown in the table below. xt4d 0 0 1 0 1 0 according to xtsl (default) 1/2 1/4 xt2d frequency division ratio aggf (msb) 0 0 1 1 0 1 0 1 31 [mv] 63 [mv] 125 [mv] 250 [mv] aggt (lsb) te/fe input conversion drr2 to drr0: partially clears the data ram values (0 write). the following values are cleared when set to 1 (on) respectively; default = 0 drr2: m08, m09, m0a drr1: m00, m01, m02 drr0: m00, m01, m02 only when lock = low note) set drr1 and drr0 for 50 s or more. asfg: when vibration detection is performed during anti-shock circuit operation, fcs servo filter is set to gain normal status. on when set to 1; default = 0 lpas: built-in analog buffer low-current consumption mode this mode reduces the total analog buffer current consumption for the vc, te, se and fe input by using a single operational amplifier. on when set to 1; default = 0 note) when using this mode, firstly check whether each error signal is properly a/d converted using the sro1 and sro0 commands of $3f. sro1, sro0: these commands are to output various data externally continuously which have been specified with the $39 command. (however, d15 (dac) of $39 must be set to 1.) digital output can be obtained from three specified pins (sock, xolt and sout) by setting these commands to 1 respectively. the default is 0, 0. the output pins for each case are shown below. sock xolt sout da13 da12 da14 da10 da09 da11 sro1 = 1 sro0 = 1 (see the description of data readout on the following page.) aghf: this halves the frequency of the internally generated sine wave during agc. cot2: the stzc signal is output from cout by setting d0 to 1. (stzc: tzc signal generated by sampling the te signal at 700khz) these settings are the same as for both focus auto gain control and tracking auto gain control. ?113 CXD2586R/-1 description of data readout sock (5.6448mhz) xolt (88.2khz) sout msb lsb ?? msb lsb ?? ?? ?? ?? ?? 16-bit register for serial/parallel conversion 16-bit register for latch sout sock xolt clk clk msb lsb to the 7-segment led to the 7-segment led data is connected to the 7-segment led by 4-bits at a time. this enable hex display using four 7-segment leds. msb lsb sout sock xolt serial data input clock input latch enable input analog output d/a to an oscilloscope, etc. offset adjustment, gain adjustment waveforms can be monitored with an oscilloscope using a serial input-type d/a converter as shown above. ?114 CXD2586R/-1 ?-20. list of servo filter coefficients ?115 CXD2586R/-1 ?116 CXD2586R/-1 ?-21. filter composition the internal filter composition is shown below. k ** and m ** indicate coefficient ram and data ram address values respectively. fcs servo gain normal; fs = 88.2khz k0d k0c k0e k10 z ? k0b z ? k09 k0a k08 z ? m04 m03 2 ? 2 ? m05 m06 z ? k11 k13 k0f fcs hold reg 1 fcs auto gain fcs pwm 2 7 fcs srch m07 2 ? k06 agfon k06 dfct fcs hold reg 2 fcs in reg sin rom fcs servo gain down; fs = 88.2khz k29 k28 k2a k2c z ? k27 z ? k25 k26 k24 z ? m04 m03 2 ? 2 ? m05 m06 z ? k2d k13 k2b fcs hold reg 1 fcs auto gain fcs pwm 2 7 fcs srch m07 2 ? k06 dfct fcs hold reg 2 fcs in reg note) set the msb bit of the k0b and k0d coefficients to 0. note) set the msb bit of the k27 and k29 coefficients to 0. ?117 CXD2586R/-1 trk servo gain normal; fs = 88.2khz k1f k1e k20 k21 z ? k1d z ? k1b k1c k1a z ? m0c m0b 2 ? 2 ? m0d m0e z ? k22 k23 trk auto gain trk pwm 2 7 trk jmp m0f 2 ? k19 agton k19 dfct trk hold reg trk in reg sin rom note) set the msb bit of the k1d and k1f coefficients to 0. trk servo gain up 1; fs = 88.2khz k3d z ? z ? k1b k3c k1a z ? m0c m0b m0e k3e k23 trk auto gain trk pwm 2 7 trk jmp m0f 2 ? k19 dfct trk hold reg trk in reg ?118 CXD2586R/-1 trk servo gain up 2; fs = 88.2khz k3b k3a k3c k3d z ? k39 z ? k37 k38 k36 z ? m0c m0b 2 ? 2 ? m0d m0e z ? k3e k23 trk auto gain trk pwm 2 7 trk jmp m0f 2 ? k19 dfct trk hold reg trk in reg note) set the msb bit of the k39 and k3b coefficients to 0. sld servo; fs = 345hz k04 k03 z ? k02 z ? k01 k00 m00 2 ? 2 ? m01 k05 k07 trk auto gain sld pwm 2 7 sld mov m02 sld in reg 2 ? note) set the msb bit of the k02 and k04 coefficients to 0. hptzc/auto gain; fs = 88.2khz k15 k17 z ? k14 m08 m09 m0a z ? auto gain reg 2 ? agton agfon agfon fcs in reg trk in reg sin rom z ? slice tzc reg slice 2 ? ?119 CXD2586R/-1 anti shock; fs = 88.2khz k34 k33 z ? z ? k31 k16 z ? m09 m08 2 ? m0a k35 comp k12 anti shock reg 2 ? trk in reg note) set the msb bit of the k34 coefficient to 0. the comparator level is 1/16 the maximum amplitude of the comparator input. avrg; fs = 88.2khz m08 avrg reg 2 ? vc, te, fe, rfdc z ? 2 ? trk hold; fs = 345hz k44 k43 z ? k42 z ? k41 k40 m18 2 ? 2 ? m19 k45 sld in reg 2 ? trk hold reg note) set the msb bit of the k42 and k44 coefficients to 0. fcs hold; fs = 345hz k4c k4b z ? k4a z ? k49 k48 m10 2 ? 2 ? m11 k4d fcs hold reg 1 fcs hold reg 2 note) set the msb bit of the k4a and k4c coefficients to 0. ?120 CXD2586R/-1 fcs servo gain normal; fs = 88.2khz, during quasi double accuracy (ex.: $3eaxx0) k0d k0c 80h k10 z ? k0b z ? 7fh k0a 81h z ? m04 m03 2 ? 2 ? m05 m06 z ? k11 k13 k0f fcs hold reg 1 fcs auto gain fcs pwm 2 7 fcs srch m07 2 ? k06 agfon k06 dfct fcs hold reg 2 fcs in reg sin rom k08 k09 2 ? 2 ? k0e 2 ? ** * * 81h, 7fh and 80h are each hex display 8-bit fixed values when set to quasi double accuracy. note) set the msb bit of the k0b and k0d coefficients during normal operation, and of the k08, k09 and k0e coefficients during quasi double accuracy to 0. fcs servo gain down; fs = 88.2khz, during quasi double accuracy (ex.: $3e5xx0) k29 k28 80h k2c z ? k27 z ? 7fh k26 81h z ? m04 m03 2 ? 2 ? m05 m06 z ? k2d k13 k2b fcs hold reg 1 fcs auto gain fcs pwm 2 7 fcs srch m07 2 ? k06 dfct fcs hold reg 2 fcs in reg k24 k25 2 ? 2 ? k2a 2 ? * * * * 81h, 7fh and 80h are each hex display 8-bit fixed values when set to quasi double accuracy. note) set the msb bit of the k27 and k29 coefficients during normal operation, and of the k24, k25 and k2a coefficients during quasi double accuracy to 0. ?121 CXD2586R/-1 trk servo gain normal; fs = 88.2khz, during quasi double accuracy (ex.: $3exax0) k1f k1e 80h k21 z ? k1d z ? 7fh k1c 81h z ? m0c m0b 2 ? 2 ? m0d m0e z ? k22 k23 trk auto gain trk pwm 2 7 trk jmp m0f 2 ? k19 agton k19 dfct trk hold reg trk in reg sin rom k1a k1b 2 ? 2 ? k20 2 ? * * * * 81h, 7fh and 80h are each hex display 8-bit fixed values when set to quasi double accuracy. note) set the msb bit of the k1d and k1f coefficients during normal operation, and of the k1a, k1b and k20 coefficients during quasi double accuracy to 0. trk servo gain up 1; fs = 88.2khz, during quasi double accuracy (ex.: $3ex5x0) k3d z ? k3c z ? 7fh 80h 81h z ? m0c m0b 2 ? m0e k3e k23 trk auto gain trk pwm 2 7 trk jmp m0f 2 ? k19 dfct trk hold reg trk in reg k1a k1b 2 ? 2 ? * * * * 81h, 7fh and 80h are each hex display 8-bit fixed values when set to quasi double accuracy. note) set the msb bit of the k1a, k1b and k3c coefficients during quasi double accuracy to 0. ?122 CXD2586R/-1 trk servo gain up 2; fs = 88.2khz, during quasi double accuracy (ex.: $3ex5x0) k3b k3a 80h k3d z ? k39 z ? 7fh k38 81h z ? m0c m0b 2 ? 2 ? m0d m0e z ? k3e k23 trk auto gain trk pwm 2 7 trk jmp m0f 2 ? k19 dfct trk hold reg trk in reg k36 k37 2 ? 2 ? k3c 2 ? * * * * 81h, 7fh and 80h are each hex display 8-bit fixed values when set to quasi double accuracy. note) set the msb bit of the k39 and k3b coefficients during normal operation, and of the k36, k37 and k3c coefficients during quasi double accuracy to 0. ?123 CXD2586R/-1 ?-22. tracking and focus frequency response f-frequency [hz] 20k 1k 100 10 2.1 ?0 0 10 20 30 40 g-gain [db] ?80 f -phase [degree] 0 180 90 ?0 focus frequency response f g f-frequency [hz] 20k 1k 100 10 2.1 ?0 0 10 20 30 40 g-gain [db] ?80 f -phase [degree] 0 180 90 ?0 tracking frequency response f g normal gain up normal gain down ?124 CXD2586R/-1 xraof c2po mnt0 mnt1 mnt2 mnt3 gnd xraof gfs xplck xugf gtop xolt sock sout wdck vc gnd spdl sled sstp +5v driver circuit gnd v cc ldon fd tg td fg vc te fe fzc rfo lock ce pdo adio v16m vc c4m c16m wfck dout sbso exck dfct mirr fsw mon cout 36 35 34 31 32 33 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 40 39 38 37 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 97 96 95 94 91 92 93 10 0 99 98 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 73 74 81 82 83 84 75 76 77 78 88 87 86 85 79 80 89 90 111 10 9 11 0 112 113 114 115 116 117 11 8 119 12 0 121 12 2 12 3 124 12 5 12 6 127 12 8 12 9 13 0 131 132 13 3 13 4 13 5 13 6 137 13 8 13 9 14 0 141 14 2 14 3 14 4 av ss 31 av ss 5 xtli xtlo av dd 5 av ss 42 lout2 ain2 av dd 4 av ss 41 nc. dv ss 1 da01 da02 da03 da04 da05 da06 se fe vc filo fili pco cltv av ss 1 rfac bias asyi asyo av dd 1 nc. dv dd 1 asye pssl wdck lrck lrcki da16 pcmdi da15 bcki da14 da13 da12 da11 da10 da09 da08 da07 lock sstp sfdr sron srdr sfon tfdr tron trdr tfon ffdr fron frdr ffon dv dd 3 vcoo vcoi test dv ss 3 tes2 tes3 nc. pdo vcki v16m av dd 2 igen av ss 2 adio rfc rfdc ce te mds mon fsw testa fok dfct mirr nc. cout c4m clok xlat data atsk dfsw sclk dirc sens sqck sqso exck sbso scor wfck mute dout md2 c16m fsto fsti mclk dts6 dts5 dts4 dts3 dts2 dts1 nc. av ss 32 av dd 3 aout1 ain1 lout1 das1 das0 xwo dts7 xtsl aout2 pwmi dv dd 2 xrst nc. dv ss 2 mcko mdp nc. vpco2 vctl vpco1 nc. pwmi sclk mute scor sqck sqso gfs clok xlat data xrst sens fok ldon gnd v dd md2 xwo ?-1. application circuit application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. ?125 CXD2586R/-1 package outline unit: mm lqfp-144p-l01 sony code eiaj code jedec code package structure package material lead treatment lead material package weight epoxy resin solder plating 42 / copper alloy lqfp-144p-l01 lqfp144-p-2020-a 1.3 g 144pin lqfp (plastic) (21.0) 0.5 0.15 0?to 10 (0.125) 0.145 0.05 0.22 0.05 (0.2) detail a detail b 1 36 37 72 73 108 109 144 0.22 0.05 0.5 m 0.1 1.7 max a b 0.1 s s 22.0 0.2 20.0 0.1 s 0.1 0.05 lqfp-144p-l021 sony code eiaj code jedec code package material lead treatment lead material package weight epoxy resin solder plating copper alloy package structure lqfp-144p-l021 lqfp144-p-2020 1.3g 144pin lqfp(plastic) 22.0 ?} 0.2 0.5 0.22 0.05 1.7 max 20.0 ?} 0.1 108 73 109 72 144 1 36 37 a detail a detail b (0.2) 0.22 0.05 (0.125) 0.145 0.05 b m 0.1 s 0.1 s s 0?to 10 0.5 0.15 (21.0) 0.1 0.05 ?126 CXD2586R/-1 sony code eiaj code jedec code package material lead treatment lead material package weight epoxy resin solder plating copper alloy package structure lqfp-144p-l081 lqfp144-p-2020 1.3g 0.5 0.22 0.05 20.0 ?} 0.1 22.0 ?} 0.2 1.7 max 144pin lqfp(plastic) 1 36 37 72 73 108 109 144 detail a 0.5 0.2 0?to 10 a detail b (0.2) 0.22 0.05 (0.15) 0.15 0.05 b m 0.1 s 0.1 s s (21.0) 0.1 0.05 lqfp-144p-l022 lqfp-144p-l081 sony code eiaj code jedec code package material lead treatment lead material package weight epoxy resin solder plating 42 / copper alloy package structure lqfp-144p-l022 lqfp144-p-2020 1.3g 144pin lqfp(plastic) 22.0 ?} 0.2 0.5 0.22 0.05 1.7 max 20.0 ?} 0.1 108 73 109 72 144 1 36 37 a detail a 0?to 10 0.5 ?} 0.15 detail b (0.2) 0.22 0.05 (0.125) 0.145 0.05 b m 0.1 s 0.1 s s (21.0) 0.1 0.05 ?127 CXD2586R/-1 lqfp-144p-l141 sony code eiaj code jedec code package material lead treatment lead material package weight epoxy resin solder plating copper alloy package structure lqfp-144p-l141 lqfp144-p-2020 1.3g 144pin lqfp(plastic) detail a 0.5 36 1 0.22 0.05 37 72 73 108 109 144 1.7 max 22.0 0.2 20.0 0.1 a detail b (0.2) 0.22 0.05 (0.15) 0.15 0.05 b m 0.1 s 0.1 s s 0.5 ?} 0.2 0?to 10 (21.0) 0.1 0.05 |
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